Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	687	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5323	1			T7	10		T35	5		T37	9
len_601_800	12356	1			T7	21		T35	17		T37	5
len_401_600	8043	1			T7	12		T35	11		T37	5
len_201_400	16391	1			T1	251		T3	1		T7	6
len_65_200	72642	1			T1	680		T32	21		T7	3
len_min_for_xof_require_squeeze	985	1			T1	10		T36	10		T40	9
len_keccak_block_sizes[72]	735	1			T1	5		T32	1		T36	5
len_keccak_block_sizes[104]	747	1			T1	5		T36	5		T40	9
len_keccak_block_sizes[136]	727	1			T1	5		T32	1		T36	5
len_keccak_block_sizes[144]	287	1			T1	5		T36	5		T75	5
len_keccak_block_sizes[168]	278	1			T1	5		T36	5		T75	5
len_datapath_width	13998	1			T1	5		T35	1		T36	5
len_2_63	210583	1			T1	1329		T2	374		T3	2
len_1	52	1			T48	1		T201	1		T72	1