Summary for Variable in_app_keymgr
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for in_app_keymgr
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
335648 | 
1 | 
 | 
 | 
T1 | 
2201 | 
 | 
T2 | 
364 | 
 | 
T3 | 
6 | 
| auto[1] | 
3391 | 
1 | 
 | 
 | 
T7 | 
12 | 
 | 
T8 | 
16 | 
 | 
T4 | 
1 | 
Summary for Variable kmac_mode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for kmac_mode
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
302976 | 
1 | 
 | 
 | 
T1 | 
2201 | 
 | 
T2 | 
364 | 
 | 
T3 | 
5 | 
| auto[1] | 
36063 | 
1 | 
 | 
 | 
T3 | 
1 | 
 | 
T32 | 
31 | 
 | 
T7 | 
57 | 
Summary for Variable sideload
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for sideload
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
325830 | 
1 | 
 | 
 | 
T1 | 
2201 | 
 | 
T2 | 
364 | 
 | 
T3 | 
6 | 
| auto[1] | 
13209 | 
1 | 
 | 
 | 
T7 | 
26 | 
 | 
T19 | 
125 | 
 | 
T8 | 
35 | 
Summary for Cross sideload_cross
Samples crossed: sideload kmac_mode in_app_keymgr
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| User Defined Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
User Defined Cross Bins for sideload_cross
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| sw_kmac_valid_sideload | 
13209 | 
1 | 
 | 
 | 
T7 | 
26 | 
 | 
T19 | 
125 | 
 | 
T8 | 
35 | 
| sw_kmac_invalid_sideload | 
325830 | 
1 | 
 | 
 | 
T1 | 
2201 | 
 | 
T2 | 
364 | 
 | 
T3 | 
6 | 
| app_valid_sideload | 
13209 | 
1 | 
 | 
 | 
T7 | 
26 | 
 | 
T19 | 
125 | 
 | 
T8 | 
35 | 
| app_invalid_sideload | 
325830 | 
1 | 
 | 
 | 
T1 | 
2201 | 
 | 
T2 | 
364 | 
 | 
T3 | 
6 |