Summary for Variable share
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for share
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
10544468 | 
1 | 
 | 
 | 
T1 | 
47900 | 
 | 
T2 | 
2992 | 
 | 
T3 | 
149 | 
| auto[1] | 
10544394 | 
1 | 
 | 
 | 
T1 | 
47900 | 
 | 
T2 | 
2992 | 
 | 
T3 | 
149 | 
Summary for Variable state_read_mask
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
4 | 
0 | 
4 | 
100.00 | 
User Defined Bins for state_read_mask
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| word_access | 
20854299 | 
1 | 
 | 
 | 
T1 | 
93928 | 
 | 
T2 | 
5984 | 
 | 
T3 | 
296 | 
| triple_byte_access | 
78039 | 
1 | 
 | 
 | 
T1 | 
620 | 
 | 
T32 | 
18 | 
 | 
T7 | 
20 | 
| halfword_access | 
78756 | 
1 | 
 | 
 | 
T1 | 
632 | 
 | 
T32 | 
18 | 
 | 
T7 | 
30 | 
| byte_access | 
77768 | 
1 | 
 | 
 | 
T1 | 
620 | 
 | 
T3 | 
2 | 
 | 
T32 | 
18 | 
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
8 | 
0 | 
8 | 
100.00 | 
 | 
Automatically Generated Cross Bins for state_mask_share_cross
Bins
| share | state_read_mask | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
word_access | 
10427186 | 
1 | 
 | 
 | 
T1 | 
46964 | 
 | 
T2 | 
2992 | 
 | 
T3 | 
148 | 
| auto[0] | 
triple_byte_access | 
39020 | 
1 | 
 | 
 | 
T1 | 
310 | 
 | 
T32 | 
9 | 
 | 
T7 | 
10 | 
| auto[0] | 
halfword_access | 
39378 | 
1 | 
 | 
 | 
T1 | 
316 | 
 | 
T32 | 
9 | 
 | 
T7 | 
15 | 
| auto[0] | 
byte_access | 
38884 | 
1 | 
 | 
 | 
T1 | 
310 | 
 | 
T3 | 
1 | 
 | 
T32 | 
9 | 
| auto[1] | 
word_access | 
10427113 | 
1 | 
 | 
 | 
T1 | 
46964 | 
 | 
T2 | 
2992 | 
 | 
T3 | 
148 | 
| auto[1] | 
triple_byte_access | 
39019 | 
1 | 
 | 
 | 
T1 | 
310 | 
 | 
T32 | 
9 | 
 | 
T7 | 
10 | 
| auto[1] | 
halfword_access | 
39378 | 
1 | 
 | 
 | 
T1 | 
316 | 
 | 
T32 | 
9 | 
 | 
T7 | 
15 | 
| auto[1] | 
byte_access | 
38884 | 
1 | 
 | 
 | 
T1 | 
310 | 
 | 
T3 | 
1 | 
 | 
T32 | 
9 |