Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	98940193	1			T2	222275		T21	5414		T7	15029
all_values[1]	98940193	1			T2	222275		T21	5414		T7	15029
all_values[2]	98940193	1			T2	222275		T21	5414		T7	15029

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

439254

1

T2

6

T21

304

T7

368

auto[1]

296381325

1

T2

666819

T21

15938

T7

44719

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

295292343

1

T2

665052

T21

16062

T7

44613

auto[1]

1528236

1

T2

1773

T21

180

T7

474

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	142220	1			T2	1		T36	14		T37	3
all_values[0]	auto[0]	auto[1]	1804	1			T2	2		T36	2		T37	4
all_values[0]	auto[1]	auto[0]	98288561	1			T2	221683		T21	5354		T7	14871
all_values[0]	auto[1]	auto[1]	507608	1			T2	589		T21	60		T7	158
all_values[1]	auto[0]	auto[0]	151093	1			T2	1		T21	150		T40	10
all_values[1]	auto[0]	auto[1]	1443	1			T2	2		T21	2		T40	3
all_values[1]	auto[1]	auto[0]	98279688	1			T2	221683		T21	5204		T7	14871
all_values[1]	auto[1]	auto[1]	507969	1			T2	589		T21	58		T7	158
all_values[2]	auto[0]	auto[0]	141214	1			T21	150		T7	365		T39	2
all_values[2]	auto[0]	auto[1]	1480	1			T21	2		T7	3		T39	1
all_values[2]	auto[1]	auto[0]	98289567	1			T2	221684		T21	5204		T7	14506
all_values[2]	auto[1]	auto[1]	507932	1			T2	591		T21	58		T7	155