Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	98940193	1			T2	222275		T21	5414		T7	15029
all_pins[1]	98940193	1			T2	222275		T21	5414		T7	15029
all_pins[2]	98940193	1			T2	222275		T21	5414		T7	15029

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	296013320	1			T2	666236		T21	16182		T7	44929
values[0x1]	807259	1			T2	589		T21	60		T7	158
transitions[0x0=>0x1]	805205	1			T2	589		T21	60		T7	158
transitions[0x1=>0x0]	805227	1			T2	589		T21	60		T7	158

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	98432585	1			T2	221686		T21	5354		T7	14871
all_pins[0]	values[0x1]	507608	1			T2	589		T21	60		T7	158
all_pins[0]	transitions[0x0=>0x1]	507594	1			T2	589		T21	60		T7	158
all_pins[0]	transitions[0x1=>0x0]	5514	1			T8	2		T22	61		T20	44
all_pins[1]	values[0x0]	98934665	1			T2	222275		T21	5414		T7	15029
all_pins[1]	values[0x1]	5528	1			T8	2		T22	61		T20	44
all_pins[1]	transitions[0x0=>0x1]	5242	1			T8	2		T22	61		T20	44
all_pins[1]	transitions[0x1=>0x0]	293837	1			T8	4439		T22	1284		T23	932
all_pins[2]	values[0x0]	98646070	1			T2	222275		T21	5414		T7	15029
all_pins[2]	values[0x1]	294123	1			T8	4439		T22	1284		T23	932
all_pins[2]	transitions[0x0=>0x1]	292369	1			T8	4407		T22	1284		T23	932
all_pins[2]	transitions[0x1=>0x0]	505876	1			T2	589		T21	60		T7	158