Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	633	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5415	1			T21	7		T7	22		T8	39
len_601_800	12133	1			T21	17		T7	43		T8	83
len_401_600	8032	1			T21	11		T7	30		T8	57
len_201_400	16220	1			T21	2		T7	5		T8	21
len_65_200	74556	1			T21	2		T7	3		T36	92
len_min_for_xof_require_squeeze	995	1			T38	9		T68	1		T52	9
len_keccak_block_sizes[72]	764	1			T36	1		T38	9		T67	1
len_keccak_block_sizes[104]	767	1			T36	1		T38	9		T40	1
len_keccak_block_sizes[136]	762	1			T38	9		T68	1		T52	9
len_keccak_block_sizes[144]	290	1			T40	1		T8	1		T41	1
len_keccak_block_sizes[168]	281	1			T36	1		T67	1		T203	5
len_datapath_width	13897	1			T36	1		T38	9		T39	246
len_2_63	213502	1			T2	390		T21	2		T7	54
len_1	47	1			T36	2		T204	1		T16	1