Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10604488 |
1 |
|
|
T2 |
2730 |
|
T21 |
6892 |
|
T7 |
19948 |
auto[1] |
10604404 |
1 |
|
|
T2 |
2730 |
|
T21 |
6892 |
|
T7 |
19948 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
20969810 |
1 |
|
|
T2 |
5460 |
|
T21 |
13720 |
|
T7 |
39728 |
triple_byte_access |
79414 |
1 |
|
|
T21 |
16 |
|
T7 |
48 |
|
T36 |
86 |
halfword_access |
80166 |
1 |
|
|
T21 |
26 |
|
T7 |
54 |
|
T36 |
72 |
byte_access |
79502 |
1 |
|
|
T21 |
22 |
|
T7 |
66 |
|
T36 |
92 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10484947 |
1 |
|
|
T2 |
2730 |
|
T21 |
6860 |
|
T7 |
19864 |
auto[0] |
triple_byte_access |
39707 |
1 |
|
|
T21 |
8 |
|
T7 |
24 |
|
T36 |
43 |
auto[0] |
halfword_access |
40083 |
1 |
|
|
T21 |
13 |
|
T7 |
27 |
|
T36 |
36 |
auto[0] |
byte_access |
39751 |
1 |
|
|
T21 |
11 |
|
T7 |
33 |
|
T36 |
46 |
auto[1] |
word_access |
10484863 |
1 |
|
|
T2 |
2730 |
|
T21 |
6860 |
|
T7 |
19864 |
auto[1] |
triple_byte_access |
39707 |
1 |
|
|
T21 |
8 |
|
T7 |
24 |
|
T36 |
43 |
auto[1] |
halfword_access |
40083 |
1 |
|
|
T21 |
13 |
|
T7 |
27 |
|
T36 |
36 |
auto[1] |
byte_access |
39751 |
1 |
|
|
T21 |
11 |
|
T7 |
33 |
|
T36 |
46 |