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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.14 97.91 92.62 99.89 76.06 95.59 99.05 97.88


Total test records in report: 1228
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T1063 /workspace/coverage/default/38.kmac_app.864044241 Jul 25 05:18:02 PM PDT 24 Jul 25 05:23:22 PM PDT 24 9893698575 ps
T1064 /workspace/coverage/default/27.kmac_test_vectors_shake_256.548914783 Jul 25 05:15:03 PM PDT 24 Jul 25 06:28:29 PM PDT 24 884699480550 ps
T1065 /workspace/coverage/default/8.kmac_entropy_ready_error.2048938812 Jul 25 05:12:51 PM PDT 24 Jul 25 05:13:02 PM PDT 24 954812592 ps
T1066 /workspace/coverage/default/37.kmac_test_vectors_sha3_256.2573412667 Jul 25 05:17:46 PM PDT 24 Jul 25 05:49:01 PM PDT 24 88128451372 ps
T1067 /workspace/coverage/default/32.kmac_sideload.2248996538 Jul 25 05:16:14 PM PDT 24 Jul 25 05:16:18 PM PDT 24 264167669 ps
T1068 /workspace/coverage/default/15.kmac_alert_test.239376718 Jul 25 05:13:53 PM PDT 24 Jul 25 05:13:54 PM PDT 24 35367226 ps
T1069 /workspace/coverage/default/15.kmac_sideload.1802452543 Jul 25 05:13:26 PM PDT 24 Jul 25 05:14:38 PM PDT 24 26351659397 ps
T1070 /workspace/coverage/default/13.kmac_sideload.28087323 Jul 25 05:13:14 PM PDT 24 Jul 25 05:16:47 PM PDT 24 27064768987 ps
T1071 /workspace/coverage/default/44.kmac_smoke.3579114285 Jul 25 05:19:31 PM PDT 24 Jul 25 05:20:49 PM PDT 24 4609518548 ps
T1072 /workspace/coverage/default/47.kmac_entropy_refresh.1929886171 Jul 25 05:20:26 PM PDT 24 Jul 25 05:26:23 PM PDT 24 36977812148 ps
T1073 /workspace/coverage/default/35.kmac_sideload.2466759317 Jul 25 05:17:02 PM PDT 24 Jul 25 05:17:21 PM PDT 24 222935232 ps
T1074 /workspace/coverage/default/32.kmac_key_error.1160846684 Jul 25 05:16:21 PM PDT 24 Jul 25 05:16:32 PM PDT 24 3030157608 ps
T1075 /workspace/coverage/default/8.kmac_entropy_refresh.1273265290 Jul 25 05:12:39 PM PDT 24 Jul 25 05:17:47 PM PDT 24 10272879078 ps
T135 /workspace/coverage/cover_reg_top/9.kmac_intr_test.2095697109 Jul 25 04:42:21 PM PDT 24 Jul 25 04:42:21 PM PDT 24 14170268 ps
T136 /workspace/coverage/cover_reg_top/43.kmac_intr_test.2875897856 Jul 25 04:42:43 PM PDT 24 Jul 25 04:42:44 PM PDT 24 14112197 ps
T198 /workspace/coverage/cover_reg_top/17.kmac_csr_rw.3127798845 Jul 25 04:43:01 PM PDT 24 Jul 25 04:43:02 PM PDT 24 38820074 ps
T160 /workspace/coverage/cover_reg_top/15.kmac_csr_rw.3720504443 Jul 25 04:42:38 PM PDT 24 Jul 25 04:42:39 PM PDT 24 151981991 ps
T91 /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.1717630821 Jul 25 04:42:54 PM PDT 24 Jul 25 04:42:55 PM PDT 24 63400070 ps
T138 /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.2232679654 Jul 25 04:42:53 PM PDT 24 Jul 25 04:42:54 PM PDT 24 83521120 ps
T137 /workspace/coverage/cover_reg_top/12.kmac_intr_test.2269169809 Jul 25 04:42:41 PM PDT 24 Jul 25 04:42:42 PM PDT 24 21453504 ps
T139 /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.276582272 Jul 25 04:42:40 PM PDT 24 Jul 25 04:42:41 PM PDT 24 160407235 ps
T132 /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.3530527004 Jul 25 04:42:42 PM PDT 24 Jul 25 04:42:48 PM PDT 24 343849438 ps
T199 /workspace/coverage/cover_reg_top/10.kmac_csr_rw.3744208564 Jul 25 04:42:42 PM PDT 24 Jul 25 04:42:43 PM PDT 24 62080304 ps
T1076 /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.1829254792 Jul 25 04:42:40 PM PDT 24 Jul 25 04:42:45 PM PDT 24 282355074 ps
T140 /workspace/coverage/cover_reg_top/14.kmac_tl_errors.2230544453 Jul 25 04:42:53 PM PDT 24 Jul 25 04:42:55 PM PDT 24 164549007 ps
T1077 /workspace/coverage/cover_reg_top/19.kmac_csr_rw.2174426998 Jul 25 04:42:45 PM PDT 24 Jul 25 04:42:46 PM PDT 24 26916933 ps
T88 /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.816983126 Jul 25 04:42:15 PM PDT 24 Jul 25 04:42:18 PM PDT 24 240515748 ps
T131 /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.3460371555 Jul 25 04:42:40 PM PDT 24 Jul 25 04:42:42 PM PDT 24 26822617 ps
T1078 /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.226271813 Jul 25 04:42:25 PM PDT 24 Jul 25 04:42:30 PM PDT 24 405059337 ps
T141 /workspace/coverage/cover_reg_top/17.kmac_tl_errors.462540032 Jul 25 04:42:44 PM PDT 24 Jul 25 04:42:45 PM PDT 24 351648111 ps
T1079 /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.1539806631 Jul 25 04:42:53 PM PDT 24 Jul 25 04:42:56 PM PDT 24 138548439 ps
T161 /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.901672353 Jul 25 04:42:16 PM PDT 24 Jul 25 04:42:19 PM PDT 24 102555749 ps
T176 /workspace/coverage/cover_reg_top/0.kmac_intr_test.1312042028 Jul 25 04:42:53 PM PDT 24 Jul 25 04:42:54 PM PDT 24 32755623 ps
T142 /workspace/coverage/cover_reg_top/10.kmac_tl_errors.3764233605 Jul 25 04:42:35 PM PDT 24 Jul 25 04:42:43 PM PDT 24 400032582 ps
T167 /workspace/coverage/cover_reg_top/40.kmac_intr_test.3962338760 Jul 25 04:42:46 PM PDT 24 Jul 25 04:42:47 PM PDT 24 38670871 ps
T162 /workspace/coverage/cover_reg_top/3.kmac_csr_rw.2589174780 Jul 25 04:42:21 PM PDT 24 Jul 25 04:42:22 PM PDT 24 33016079 ps
T133 /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.3200167960 Jul 25 04:42:14 PM PDT 24 Jul 25 04:42:19 PM PDT 24 381606006 ps
T1080 /workspace/coverage/cover_reg_top/2.kmac_csr_rw.4272074945 Jul 25 04:42:10 PM PDT 24 Jul 25 04:42:11 PM PDT 24 136705322 ps
T179 /workspace/coverage/cover_reg_top/38.kmac_intr_test.1947479398 Jul 25 04:42:51 PM PDT 24 Jul 25 04:42:52 PM PDT 24 15336547 ps
T152 /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.3590552821 Jul 25 04:42:47 PM PDT 24 Jul 25 04:42:49 PM PDT 24 24096373 ps
T1081 /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.876009028 Jul 25 04:42:20 PM PDT 24 Jul 25 04:42:23 PM PDT 24 277666365 ps
T1082 /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.249704574 Jul 25 04:42:37 PM PDT 24 Jul 25 04:42:41 PM PDT 24 886597694 ps
T1083 /workspace/coverage/cover_reg_top/2.kmac_mem_walk.1047303947 Jul 25 04:42:54 PM PDT 24 Jul 25 04:42:55 PM PDT 24 18549048 ps
T168 /workspace/coverage/cover_reg_top/3.kmac_intr_test.3897461057 Jul 25 04:42:50 PM PDT 24 Jul 25 04:42:51 PM PDT 24 16088009 ps
T1084 /workspace/coverage/cover_reg_top/44.kmac_intr_test.2880619450 Jul 25 04:43:01 PM PDT 24 Jul 25 04:43:12 PM PDT 24 14288519 ps
T1085 /workspace/coverage/cover_reg_top/19.kmac_intr_test.1203279819 Jul 25 04:42:47 PM PDT 24 Jul 25 04:42:49 PM PDT 24 40726661 ps
T89 /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.2822042485 Jul 25 04:42:31 PM PDT 24 Jul 25 04:42:32 PM PDT 24 36674246 ps
T163 /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.248846135 Jul 25 04:42:46 PM PDT 24 Jul 25 04:42:48 PM PDT 24 161817359 ps
T169 /workspace/coverage/cover_reg_top/5.kmac_intr_test.2813509022 Jul 25 04:42:25 PM PDT 24 Jul 25 04:42:26 PM PDT 24 14079660 ps
T170 /workspace/coverage/cover_reg_top/11.kmac_intr_test.103552891 Jul 25 04:42:51 PM PDT 24 Jul 25 04:42:52 PM PDT 24 74128214 ps
T154 /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.148339112 Jul 25 04:42:25 PM PDT 24 Jul 25 04:42:31 PM PDT 24 51710522 ps
T164 /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.2662541159 Jul 25 04:42:44 PM PDT 24 Jul 25 04:42:47 PM PDT 24 394387998 ps
T180 /workspace/coverage/cover_reg_top/1.kmac_intr_test.826520745 Jul 25 04:42:14 PM PDT 24 Jul 25 04:42:20 PM PDT 24 27128157 ps
T1086 /workspace/coverage/cover_reg_top/9.kmac_tl_errors.3918517297 Jul 25 04:42:29 PM PDT 24 Jul 25 04:42:32 PM PDT 24 59546469 ps
T1087 /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.2196427407 Jul 25 04:42:42 PM PDT 24 Jul 25 04:42:43 PM PDT 24 24244680 ps
T181 /workspace/coverage/cover_reg_top/18.kmac_intr_test.291461290 Jul 25 04:42:45 PM PDT 24 Jul 25 04:42:46 PM PDT 24 64108737 ps
T1088 /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.3574865678 Jul 25 04:42:42 PM PDT 24 Jul 25 04:42:44 PM PDT 24 41075370 ps
T165 /workspace/coverage/cover_reg_top/18.kmac_csr_rw.2553473840 Jul 25 04:42:44 PM PDT 24 Jul 25 04:42:46 PM PDT 24 38255757 ps
T134 /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.3276888998 Jul 25 04:42:38 PM PDT 24 Jul 25 04:42:41 PM PDT 24 669042245 ps
T186 /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.40710994 Jul 25 04:42:45 PM PDT 24 Jul 25 04:42:48 PM PDT 24 337197069 ps
T97 /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.1290698417 Jul 25 04:42:44 PM PDT 24 Jul 25 04:42:47 PM PDT 24 182592536 ps
T1089 /workspace/coverage/cover_reg_top/15.kmac_tl_errors.3902180460 Jul 25 04:42:28 PM PDT 24 Jul 25 04:42:29 PM PDT 24 22222390 ps
T1090 /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.1503765658 Jul 25 04:42:53 PM PDT 24 Jul 25 04:43:01 PM PDT 24 615396004 ps
T1091 /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.4211816096 Jul 25 04:42:25 PM PDT 24 Jul 25 04:42:27 PM PDT 24 49037530 ps
T166 /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.3367896362 Jul 25 04:42:30 PM PDT 24 Jul 25 04:42:41 PM PDT 24 3013853522 ps
T1092 /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.1481327662 Jul 25 04:42:48 PM PDT 24 Jul 25 04:42:50 PM PDT 24 61767418 ps
T188 /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.1901699834 Jul 25 04:42:35 PM PDT 24 Jul 25 04:42:38 PM PDT 24 188800839 ps
T1093 /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.513274429 Jul 25 04:42:53 PM PDT 24 Jul 25 04:42:54 PM PDT 24 23050829 ps
T1094 /workspace/coverage/cover_reg_top/19.kmac_tl_errors.3121541752 Jul 25 04:42:48 PM PDT 24 Jul 25 04:42:50 PM PDT 24 795476923 ps
T1095 /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.2767697813 Jul 25 04:42:14 PM PDT 24 Jul 25 04:42:15 PM PDT 24 76288777 ps
T90 /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1261942921 Jul 25 04:42:35 PM PDT 24 Jul 25 04:42:37 PM PDT 24 26152426 ps
T94 /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.4200870309 Jul 25 04:42:50 PM PDT 24 Jul 25 04:42:52 PM PDT 24 156932406 ps
T1096 /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.2087914285 Jul 25 04:42:13 PM PDT 24 Jul 25 04:42:14 PM PDT 24 45552985 ps
T96 /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.3292711225 Jul 25 04:42:24 PM PDT 24 Jul 25 04:42:26 PM PDT 24 45516616 ps
T92 /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.1786643976 Jul 25 04:42:24 PM PDT 24 Jul 25 04:42:31 PM PDT 24 74121173 ps
T177 /workspace/coverage/cover_reg_top/41.kmac_intr_test.1707458135 Jul 25 04:43:01 PM PDT 24 Jul 25 04:43:02 PM PDT 24 29358616 ps
T1097 /workspace/coverage/cover_reg_top/30.kmac_intr_test.3502773196 Jul 25 04:43:02 PM PDT 24 Jul 25 04:43:13 PM PDT 24 25925084 ps
T1098 /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.212415475 Jul 25 04:42:38 PM PDT 24 Jul 25 04:42:40 PM PDT 24 37852531 ps
T1099 /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.2334729470 Jul 25 04:42:50 PM PDT 24 Jul 25 04:42:51 PM PDT 24 26373482 ps
T1100 /workspace/coverage/cover_reg_top/16.kmac_intr_test.431356461 Jul 25 04:42:43 PM PDT 24 Jul 25 04:42:44 PM PDT 24 28935163 ps
T1101 /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.2394180315 Jul 25 04:42:47 PM PDT 24 Jul 25 04:42:49 PM PDT 24 78147275 ps
T1102 /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.1645003872 Jul 25 04:42:56 PM PDT 24 Jul 25 04:43:04 PM PDT 24 144081982 ps
T178 /workspace/coverage/cover_reg_top/24.kmac_intr_test.19549059 Jul 25 04:43:00 PM PDT 24 Jul 25 04:43:01 PM PDT 24 18887156 ps
T1103 /workspace/coverage/cover_reg_top/15.kmac_intr_test.3815665812 Jul 25 04:42:25 PM PDT 24 Jul 25 04:42:26 PM PDT 24 15529878 ps
T171 /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.1782507937 Jul 25 04:42:13 PM PDT 24 Jul 25 04:42:15 PM PDT 24 111893701 ps
T1104 /workspace/coverage/cover_reg_top/0.kmac_csr_rw.521306959 Jul 25 04:42:11 PM PDT 24 Jul 25 04:42:13 PM PDT 24 12963043 ps
T1105 /workspace/coverage/cover_reg_top/45.kmac_intr_test.860955352 Jul 25 04:43:01 PM PDT 24 Jul 25 04:43:02 PM PDT 24 15294476 ps
T1106 /workspace/coverage/cover_reg_top/48.kmac_intr_test.869225619 Jul 25 04:43:01 PM PDT 24 Jul 25 04:43:02 PM PDT 24 137392041 ps
T1107 /workspace/coverage/cover_reg_top/0.kmac_mem_walk.2274110947 Jul 25 04:42:11 PM PDT 24 Jul 25 04:42:12 PM PDT 24 11962495 ps
T1108 /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.2951396110 Jul 25 04:42:58 PM PDT 24 Jul 25 04:43:01 PM PDT 24 376673897 ps
T172 /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.1896475172 Jul 25 04:42:42 PM PDT 24 Jul 25 04:42:44 PM PDT 24 199624153 ps
T190 /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.1692311234 Jul 25 04:42:12 PM PDT 24 Jul 25 04:42:17 PM PDT 24 272471252 ps
T1109 /workspace/coverage/cover_reg_top/7.kmac_intr_test.700093852 Jul 25 04:42:45 PM PDT 24 Jul 25 04:42:46 PM PDT 24 13411298 ps
T95 /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.3129752676 Jul 25 04:42:09 PM PDT 24 Jul 25 04:42:10 PM PDT 24 17224457 ps
T1110 /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.4107443809 Jul 25 04:42:52 PM PDT 24 Jul 25 04:42:55 PM PDT 24 75352155 ps
T155 /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.51823368 Jul 25 04:42:19 PM PDT 24 Jul 25 04:42:21 PM PDT 24 106440027 ps
T187 /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.710008254 Jul 25 04:42:53 PM PDT 24 Jul 25 04:42:59 PM PDT 24 196884053 ps
T1111 /workspace/coverage/cover_reg_top/33.kmac_intr_test.378155581 Jul 25 04:42:50 PM PDT 24 Jul 25 04:42:51 PM PDT 24 24813837 ps
T1112 /workspace/coverage/cover_reg_top/16.kmac_csr_rw.3666721540 Jul 25 04:43:00 PM PDT 24 Jul 25 04:43:01 PM PDT 24 32195885 ps
T1113 /workspace/coverage/cover_reg_top/10.kmac_intr_test.3361524857 Jul 25 04:42:36 PM PDT 24 Jul 25 04:42:37 PM PDT 24 43795662 ps
T173 /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.1839580710 Jul 25 04:42:41 PM PDT 24 Jul 25 04:42:43 PM PDT 24 53653201 ps
T195 /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.3230935806 Jul 25 04:42:20 PM PDT 24 Jul 25 04:42:24 PM PDT 24 175014201 ps
T1114 /workspace/coverage/cover_reg_top/21.kmac_intr_test.2793916216 Jul 25 04:42:59 PM PDT 24 Jul 25 04:43:00 PM PDT 24 14692688 ps
T1115 /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.3341925723 Jul 25 04:42:45 PM PDT 24 Jul 25 04:42:48 PM PDT 24 36641706 ps
T197 /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.2947154287 Jul 25 04:42:51 PM PDT 24 Jul 25 04:42:52 PM PDT 24 29766023 ps
T1116 /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.2018319790 Jul 25 04:43:00 PM PDT 24 Jul 25 04:43:02 PM PDT 24 50188336 ps
T1117 /workspace/coverage/cover_reg_top/26.kmac_intr_test.2055411800 Jul 25 04:42:48 PM PDT 24 Jul 25 04:42:50 PM PDT 24 17198317 ps
T1118 /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.4167550053 Jul 25 04:42:36 PM PDT 24 Jul 25 04:42:37 PM PDT 24 19062181 ps
T1119 /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.3725091382 Jul 25 04:42:20 PM PDT 24 Jul 25 04:42:22 PM PDT 24 49654470 ps
T1120 /workspace/coverage/cover_reg_top/5.kmac_tl_errors.4041643568 Jul 25 04:42:15 PM PDT 24 Jul 25 04:42:19 PM PDT 24 314977268 ps
T1121 /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.662772957 Jul 25 04:42:48 PM PDT 24 Jul 25 04:42:50 PM PDT 24 165901542 ps
T1122 /workspace/coverage/cover_reg_top/7.kmac_tl_errors.819691479 Jul 25 04:42:55 PM PDT 24 Jul 25 04:42:58 PM PDT 24 604871603 ps
T1123 /workspace/coverage/cover_reg_top/14.kmac_intr_test.1362707775 Jul 25 04:42:49 PM PDT 24 Jul 25 04:42:50 PM PDT 24 60804893 ps
T1124 /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.4129582622 Jul 25 04:42:22 PM PDT 24 Jul 25 04:42:24 PM PDT 24 23840448 ps
T191 /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.3214640142 Jul 25 04:42:29 PM PDT 24 Jul 25 04:42:32 PM PDT 24 249495148 ps
T1125 /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.1054397849 Jul 25 04:42:21 PM PDT 24 Jul 25 04:42:23 PM PDT 24 71240792 ps
T1126 /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.880826641 Jul 25 04:42:32 PM PDT 24 Jul 25 04:42:33 PM PDT 24 28737333 ps
T93 /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.2109340999 Jul 25 04:42:42 PM PDT 24 Jul 25 04:42:44 PM PDT 24 57974903 ps
T1127 /workspace/coverage/cover_reg_top/25.kmac_intr_test.498204142 Jul 25 04:42:47 PM PDT 24 Jul 25 04:42:48 PM PDT 24 28715732 ps
T1128 /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.1400419792 Jul 25 04:42:24 PM PDT 24 Jul 25 04:42:29 PM PDT 24 234573890 ps
T1129 /workspace/coverage/cover_reg_top/35.kmac_intr_test.2106019715 Jul 25 04:42:52 PM PDT 24 Jul 25 04:42:53 PM PDT 24 19854526 ps
T1130 /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.4036407039 Jul 25 04:42:17 PM PDT 24 Jul 25 04:42:18 PM PDT 24 91105346 ps
T1131 /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.2416798040 Jul 25 04:42:44 PM PDT 24 Jul 25 04:42:45 PM PDT 24 62961349 ps
T1132 /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.507995903 Jul 25 04:42:32 PM PDT 24 Jul 25 04:42:33 PM PDT 24 38311323 ps
T192 /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.663332892 Jul 25 04:42:34 PM PDT 24 Jul 25 04:42:38 PM PDT 24 61132182 ps
T1133 /workspace/coverage/cover_reg_top/28.kmac_intr_test.1998150692 Jul 25 04:42:53 PM PDT 24 Jul 25 04:42:54 PM PDT 24 28044574 ps
T1134 /workspace/coverage/cover_reg_top/4.kmac_csr_rw.3380409553 Jul 25 04:42:42 PM PDT 24 Jul 25 04:42:43 PM PDT 24 73085373 ps
T1135 /workspace/coverage/cover_reg_top/9.kmac_csr_rw.1853387176 Jul 25 04:42:53 PM PDT 24 Jul 25 04:42:54 PM PDT 24 184964402 ps
T1136 /workspace/coverage/cover_reg_top/6.kmac_intr_test.3499307235 Jul 25 04:42:18 PM PDT 24 Jul 25 04:42:18 PM PDT 24 11468592 ps
T1137 /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.3225517815 Jul 25 04:42:29 PM PDT 24 Jul 25 04:42:37 PM PDT 24 148821622 ps
T1138 /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.1682670835 Jul 25 04:42:29 PM PDT 24 Jul 25 04:42:31 PM PDT 24 121761704 ps
T1139 /workspace/coverage/cover_reg_top/31.kmac_intr_test.3774742041 Jul 25 04:43:00 PM PDT 24 Jul 25 04:43:01 PM PDT 24 19006799 ps
T1140 /workspace/coverage/cover_reg_top/3.kmac_tl_errors.3757091813 Jul 25 04:42:11 PM PDT 24 Jul 25 04:42:13 PM PDT 24 86406377 ps
T1141 /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.3155205815 Jul 25 04:42:12 PM PDT 24 Jul 25 04:42:14 PM PDT 24 226059614 ps
T1142 /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.14533664 Jul 25 04:42:48 PM PDT 24 Jul 25 04:42:50 PM PDT 24 369718711 ps
T1143 /workspace/coverage/cover_reg_top/49.kmac_intr_test.374394278 Jul 25 04:43:03 PM PDT 24 Jul 25 04:43:04 PM PDT 24 11689564 ps
T189 /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.504783251 Jul 25 04:42:49 PM PDT 24 Jul 25 04:42:53 PM PDT 24 189012948 ps
T1144 /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.78436361 Jul 25 04:42:47 PM PDT 24 Jul 25 04:42:49 PM PDT 24 157367698 ps
T156 /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.2794371309 Jul 25 04:42:14 PM PDT 24 Jul 25 04:42:16 PM PDT 24 97210322 ps
T1145 /workspace/coverage/cover_reg_top/1.kmac_tl_errors.3952492081 Jul 25 04:42:13 PM PDT 24 Jul 25 04:42:16 PM PDT 24 375493620 ps
T1146 /workspace/coverage/cover_reg_top/32.kmac_intr_test.460924729 Jul 25 04:42:52 PM PDT 24 Jul 25 04:42:53 PM PDT 24 23809516 ps
T1147 /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.3287061250 Jul 25 04:42:28 PM PDT 24 Jul 25 04:42:30 PM PDT 24 62054914 ps
T157 /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.3673711074 Jul 25 04:42:13 PM PDT 24 Jul 25 04:42:14 PM PDT 24 26748625 ps
T1148 /workspace/coverage/cover_reg_top/13.kmac_tl_errors.640624108 Jul 25 04:42:45 PM PDT 24 Jul 25 04:42:48 PM PDT 24 294441369 ps
T1149 /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.2294589809 Jul 25 04:42:53 PM PDT 24 Jul 25 04:42:55 PM PDT 24 61094656 ps
T1150 /workspace/coverage/cover_reg_top/16.kmac_tl_errors.609335259 Jul 25 04:42:48 PM PDT 24 Jul 25 04:42:50 PM PDT 24 52035930 ps
T1151 /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.2653681166 Jul 25 04:42:13 PM PDT 24 Jul 25 04:42:14 PM PDT 24 28989115 ps
T1152 /workspace/coverage/cover_reg_top/8.kmac_tl_errors.4188088713 Jul 25 04:42:33 PM PDT 24 Jul 25 04:42:36 PM PDT 24 144163418 ps
T1153 /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.2509151664 Jul 25 04:42:47 PM PDT 24 Jul 25 04:42:57 PM PDT 24 896638307 ps
T1154 /workspace/coverage/cover_reg_top/18.kmac_tl_errors.107731865 Jul 25 04:42:37 PM PDT 24 Jul 25 04:42:38 PM PDT 24 59760546 ps
T158 /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.3972130709 Jul 25 04:42:19 PM PDT 24 Jul 25 04:42:21 PM PDT 24 35702798 ps
T1155 /workspace/coverage/cover_reg_top/42.kmac_intr_test.602551989 Jul 25 04:42:45 PM PDT 24 Jul 25 04:42:45 PM PDT 24 31390457 ps
T1156 /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.4216173977 Jul 25 04:42:48 PM PDT 24 Jul 25 04:42:51 PM PDT 24 268884963 ps
T1157 /workspace/coverage/cover_reg_top/37.kmac_intr_test.4003081486 Jul 25 04:42:46 PM PDT 24 Jul 25 04:42:47 PM PDT 24 92178175 ps
T1158 /workspace/coverage/cover_reg_top/2.kmac_tl_errors.1749084848 Jul 25 04:42:14 PM PDT 24 Jul 25 04:42:17 PM PDT 24 206447036 ps
T1159 /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.53692101 Jul 25 04:42:45 PM PDT 24 Jul 25 04:42:47 PM PDT 24 270965409 ps
T1160 /workspace/coverage/cover_reg_top/12.kmac_csr_rw.1836566786 Jul 25 04:42:32 PM PDT 24 Jul 25 04:42:38 PM PDT 24 59722389 ps
T1161 /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.1163218325 Jul 25 04:42:58 PM PDT 24 Jul 25 04:43:03 PM PDT 24 227894798 ps
T1162 /workspace/coverage/cover_reg_top/14.kmac_csr_rw.4266891599 Jul 25 04:42:54 PM PDT 24 Jul 25 04:42:56 PM PDT 24 32141612 ps
T1163 /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.3648936349 Jul 25 04:42:58 PM PDT 24 Jul 25 04:43:00 PM PDT 24 44338489 ps
T1164 /workspace/coverage/cover_reg_top/0.kmac_tl_errors.937991241 Jul 25 04:42:19 PM PDT 24 Jul 25 04:42:22 PM PDT 24 135520089 ps
T1165 /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.393191266 Jul 25 04:42:55 PM PDT 24 Jul 25 04:42:56 PM PDT 24 28690624 ps
T1166 /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.1390181534 Jul 25 04:42:44 PM PDT 24 Jul 25 04:42:46 PM PDT 24 70508118 ps
T1167 /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.930844909 Jul 25 04:42:48 PM PDT 24 Jul 25 04:42:50 PM PDT 24 29590939 ps
T1168 /workspace/coverage/cover_reg_top/8.kmac_csr_rw.525116719 Jul 25 04:42:29 PM PDT 24 Jul 25 04:42:30 PM PDT 24 36712190 ps
T1169 /workspace/coverage/cover_reg_top/17.kmac_intr_test.1533780927 Jul 25 04:42:38 PM PDT 24 Jul 25 04:42:39 PM PDT 24 16840190 ps
T1170 /workspace/coverage/cover_reg_top/22.kmac_intr_test.814568797 Jul 25 04:42:49 PM PDT 24 Jul 25 04:42:55 PM PDT 24 16278959 ps
T1171 /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.1344165879 Jul 25 04:42:38 PM PDT 24 Jul 25 04:42:40 PM PDT 24 93489581 ps
T1172 /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.2723857108 Jul 25 04:42:35 PM PDT 24 Jul 25 04:42:38 PM PDT 24 290658776 ps
T1173 /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.3954732118 Jul 25 04:42:48 PM PDT 24 Jul 25 04:42:51 PM PDT 24 188354345 ps
T1174 /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.4280664819 Jul 25 04:42:15 PM PDT 24 Jul 25 04:42:17 PM PDT 24 60862174 ps
T1175 /workspace/coverage/cover_reg_top/5.kmac_csr_rw.3302191181 Jul 25 04:42:39 PM PDT 24 Jul 25 04:42:40 PM PDT 24 40679439 ps
T1176 /workspace/coverage/cover_reg_top/29.kmac_intr_test.846822823 Jul 25 04:42:54 PM PDT 24 Jul 25 04:42:55 PM PDT 24 57170179 ps
T1177 /workspace/coverage/cover_reg_top/1.kmac_csr_rw.3964714363 Jul 25 04:42:54 PM PDT 24 Jul 25 04:42:55 PM PDT 24 100455397 ps
T1178 /workspace/coverage/cover_reg_top/13.kmac_intr_test.3036090732 Jul 25 04:42:53 PM PDT 24 Jul 25 04:42:54 PM PDT 24 100213054 ps
T196 /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.3352696446 Jul 25 04:42:27 PM PDT 24 Jul 25 04:42:30 PM PDT 24 247160610 ps
T194 /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.4058578285 Jul 25 04:42:48 PM PDT 24 Jul 25 04:42:53 PM PDT 24 363266451 ps
T1179 /workspace/coverage/cover_reg_top/11.kmac_tl_errors.2356139686 Jul 25 04:42:43 PM PDT 24 Jul 25 04:42:46 PM PDT 24 150155284 ps
T1180 /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.585717604 Jul 25 04:42:54 PM PDT 24 Jul 25 04:42:56 PM PDT 24 239646365 ps
T1181 /workspace/coverage/cover_reg_top/23.kmac_intr_test.3005034894 Jul 25 04:42:44 PM PDT 24 Jul 25 04:42:45 PM PDT 24 66728439 ps
T1182 /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.4193342301 Jul 25 04:42:25 PM PDT 24 Jul 25 04:42:27 PM PDT 24 89596546 ps
T1183 /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.2205837868 Jul 25 04:42:29 PM PDT 24 Jul 25 04:42:34 PM PDT 24 265599794 ps
T1184 /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.999204192 Jul 25 04:42:53 PM PDT 24 Jul 25 04:42:55 PM PDT 24 100320010 ps
T1185 /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.2480920101 Jul 25 04:42:58 PM PDT 24 Jul 25 04:43:00 PM PDT 24 45874152 ps
T1186 /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.506191227 Jul 25 04:42:16 PM PDT 24 Jul 25 04:42:18 PM PDT 24 183714370 ps
T1187 /workspace/coverage/cover_reg_top/34.kmac_intr_test.2138587228 Jul 25 04:42:51 PM PDT 24 Jul 25 04:42:52 PM PDT 24 52074912 ps
T1188 /workspace/coverage/cover_reg_top/7.kmac_csr_rw.3592851095 Jul 25 04:42:36 PM PDT 24 Jul 25 04:42:37 PM PDT 24 17516859 ps
T1189 /workspace/coverage/cover_reg_top/36.kmac_intr_test.4196921263 Jul 25 04:42:57 PM PDT 24 Jul 25 04:42:58 PM PDT 24 18013695 ps
T1190 /workspace/coverage/cover_reg_top/3.kmac_mem_walk.1853825321 Jul 25 04:42:21 PM PDT 24 Jul 25 04:42:22 PM PDT 24 18951699 ps
T1191 /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.115735667 Jul 25 04:42:40 PM PDT 24 Jul 25 04:42:41 PM PDT 24 28163719 ps
T1192 /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.1618493150 Jul 25 04:42:47 PM PDT 24 Jul 25 04:42:48 PM PDT 24 76160246 ps
T1193 /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.234497472 Jul 25 04:42:48 PM PDT 24 Jul 25 04:42:49 PM PDT 24 19092995 ps
T1194 /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.86107846 Jul 25 04:42:43 PM PDT 24 Jul 25 04:42:44 PM PDT 24 40419695 ps
T1195 /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.1113828453 Jul 25 04:43:05 PM PDT 24 Jul 25 04:43:07 PM PDT 24 60686761 ps
T1196 /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.443509905 Jul 25 04:42:47 PM PDT 24 Jul 25 04:42:48 PM PDT 24 262826503 ps
T1197 /workspace/coverage/cover_reg_top/12.kmac_tl_errors.1057845157 Jul 25 04:42:47 PM PDT 24 Jul 25 04:42:50 PM PDT 24 126038236 ps
T1198 /workspace/coverage/cover_reg_top/6.kmac_tl_errors.1748637648 Jul 25 04:42:16 PM PDT 24 Jul 25 04:42:18 PM PDT 24 71319493 ps
T1199 /workspace/coverage/cover_reg_top/4.kmac_intr_test.1610472240 Jul 25 04:42:59 PM PDT 24 Jul 25 04:43:00 PM PDT 24 40967552 ps
T1200 /workspace/coverage/cover_reg_top/4.kmac_tl_errors.492835391 Jul 25 04:42:48 PM PDT 24 Jul 25 04:42:52 PM PDT 24 132691169 ps
T1201 /workspace/coverage/cover_reg_top/13.kmac_csr_rw.1769870948 Jul 25 04:42:35 PM PDT 24 Jul 25 04:42:36 PM PDT 24 175232895 ps
T1202 /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.406042312 Jul 25 04:42:44 PM PDT 24 Jul 25 04:42:45 PM PDT 24 19056523 ps
T1203 /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.601044992 Jul 25 04:42:45 PM PDT 24 Jul 25 04:42:48 PM PDT 24 196112032 ps
T1204 /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.1265634766 Jul 25 04:42:43 PM PDT 24 Jul 25 04:42:45 PM PDT 24 24861647 ps
T193 /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.3132641204 Jul 25 04:42:46 PM PDT 24 Jul 25 04:42:48 PM PDT 24 104839508 ps
T1205 /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.1911874052 Jul 25 04:42:45 PM PDT 24 Jul 25 04:42:48 PM PDT 24 81055254 ps
T1206 /workspace/coverage/cover_reg_top/2.kmac_intr_test.3937202517 Jul 25 04:42:32 PM PDT 24 Jul 25 04:42:33 PM PDT 24 19693096 ps
T1207 /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.3924248298 Jul 25 04:42:33 PM PDT 24 Jul 25 04:42:39 PM PDT 24 41779171 ps
T1208 /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.1965966225 Jul 25 04:42:53 PM PDT 24 Jul 25 04:42:58 PM PDT 24 853348280 ps
T1209 /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.2317624876 Jul 25 04:42:24 PM PDT 24 Jul 25 04:42:28 PM PDT 24 140575080 ps
T1210 /workspace/coverage/cover_reg_top/4.kmac_mem_walk.405021961 Jul 25 04:42:26 PM PDT 24 Jul 25 04:42:28 PM PDT 24 17439266 ps
T1211 /workspace/coverage/cover_reg_top/39.kmac_intr_test.1232675976 Jul 25 04:42:49 PM PDT 24 Jul 25 04:42:50 PM PDT 24 21631426 ps
T1212 /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.2809361128 Jul 25 04:42:46 PM PDT 24 Jul 25 04:42:54 PM PDT 24 373185513 ps
T1213 /workspace/coverage/cover_reg_top/20.kmac_intr_test.718206553 Jul 25 04:42:57 PM PDT 24 Jul 25 04:42:58 PM PDT 24 39423822 ps
T1214 /workspace/coverage/cover_reg_top/27.kmac_intr_test.1688952491 Jul 25 04:42:56 PM PDT 24 Jul 25 04:42:57 PM PDT 24 16960385 ps
T1215 /workspace/coverage/cover_reg_top/46.kmac_intr_test.297402238 Jul 25 04:43:01 PM PDT 24 Jul 25 04:43:01 PM PDT 24 22848945 ps
T1216 /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.2319356053 Jul 25 04:42:42 PM PDT 24 Jul 25 04:42:45 PM PDT 24 65694777 ps
T1217 /workspace/coverage/cover_reg_top/8.kmac_intr_test.3055572929 Jul 25 04:42:11 PM PDT 24 Jul 25 04:42:12 PM PDT 24 28324071 ps
T1218 /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.2600074088 Jul 25 04:42:29 PM PDT 24 Jul 25 04:42:32 PM PDT 24 52363690 ps
T1219 /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.1370011575 Jul 25 04:42:25 PM PDT 24 Jul 25 04:42:26 PM PDT 24 65072100 ps
T1220 /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.2845505941 Jul 25 04:42:26 PM PDT 24 Jul 25 04:42:27 PM PDT 24 54831553 ps
T1221 /workspace/coverage/cover_reg_top/1.kmac_mem_walk.1018132909 Jul 25 04:42:14 PM PDT 24 Jul 25 04:42:15 PM PDT 24 16438814 ps
T1222 /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.1969964626 Jul 25 04:42:54 PM PDT 24 Jul 25 04:43:04 PM PDT 24 515695957 ps
T1223 /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.2869623783 Jul 25 04:42:42 PM PDT 24 Jul 25 04:42:46 PM PDT 24 368746957 ps
T1224 /workspace/coverage/cover_reg_top/11.kmac_csr_rw.3651038943 Jul 25 04:42:23 PM PDT 24 Jul 25 04:42:24 PM PDT 24 61785929 ps
T1225 /workspace/coverage/cover_reg_top/47.kmac_intr_test.3867050105 Jul 25 04:43:01 PM PDT 24 Jul 25 04:43:02 PM PDT 24 32700975 ps
T1226 /workspace/coverage/cover_reg_top/6.kmac_csr_rw.1495487148 Jul 25 04:42:25 PM PDT 24 Jul 25 04:42:26 PM PDT 24 29981103 ps
T1227 /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.3855026113 Jul 25 04:42:14 PM PDT 24 Jul 25 04:42:19 PM PDT 24 188117403 ps
T1228 /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.1073427619 Jul 25 04:42:41 PM PDT 24 Jul 25 04:42:43 PM PDT 24 38668422 ps

Test location /workspace/coverage/default/45.kmac_app.2639645665
Short name T7
Test name
Test status
Simulation time 50783111664 ps
CPU time 310.71 seconds
Started Jul 25 05:19:52 PM PDT 24
Finished Jul 25 05:25:03 PM PDT 24
Peak memory 247496 kb
Host smart-030e03e1-5c68-473d-857b-0333060f7ea2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639645665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.2639645665 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/45.kmac_app/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.3530527004
Short name T132
Test name
Test status
Simulation time 343849438 ps
CPU time 5.11 seconds
Started Jul 25 04:42:42 PM PDT 24
Finished Jul 25 04:42:48 PM PDT 24
Peak memory 215840 kb
Host smart-796d3e2f-44d3-41f0-9a38-0b027fbe4606
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530527004 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.35305
27004 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/12.kmac_error.4238221650
Short name T22
Test name
Test status
Simulation time 19249193967 ps
CPU time 404.08 seconds
Started Jul 25 05:13:13 PM PDT 24
Finished Jul 25 05:19:58 PM PDT 24
Peak memory 274948 kb
Host smart-f12e472f-b57c-47e1-b8cc-3646c66c5972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238221650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.4238221650 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_error/latest

Test location /workspace/coverage/default/2.kmac_sec_cm.1713927741
Short name T31
Test name
Test status
Simulation time 40146563356 ps
CPU time 125.14 seconds
Started Jul 25 05:12:15 PM PDT 24
Finished Jul 25 05:14:20 PM PDT 24
Peak memory 308204 kb
Host smart-7d695bc9-0d9b-4e8c-98ec-fea81423e5a4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713927741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.1713927741 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/2.kmac_sec_cm/latest

Test location /workspace/coverage/default/16.kmac_stress_all.2356663115
Short name T8
Test name
Test status
Simulation time 26151448946 ps
CPU time 961.79 seconds
Started Jul 25 05:13:39 PM PDT 24
Finished Jul 25 05:29:41 PM PDT 24
Peak memory 308832 kb
Host smart-2854437d-5082-4fb5-a8a2-f35331fb4b48
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2356663115 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.2356663115 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_stress_all/latest

Test location /workspace/coverage/default/9.kmac_stress_all_with_rand_reset.4222159634
Short name T50
Test name
Test status
Simulation time 82065635418 ps
CPU time 4101.77 seconds
Started Jul 25 05:12:56 PM PDT 24
Finished Jul 25 06:21:18 PM PDT 24
Peak memory 513432 kb
Host smart-26e7a7ff-b947-4b67-ab4d-916145b5aa98
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4222159634 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all_with_rand_reset.4222159634 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.kmac_lc_escalation.1906146336
Short name T34
Test name
Test status
Simulation time 38981074 ps
CPU time 1.36 seconds
Started Jul 25 05:14:57 PM PDT 24
Finished Jul 25 05:14:59 PM PDT 24
Peak memory 226636 kb
Host smart-4baa9064-7218-4c4f-81b8-95f81dbda2f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906146336 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.1906146336 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/25.kmac_lc_escalation/latest

Test location /workspace/coverage/default/27.kmac_key_error.3002632981
Short name T5
Test name
Test status
Simulation time 588706983 ps
CPU time 5.17 seconds
Started Jul 25 05:15:07 PM PDT 24
Finished Jul 25 05:15:12 PM PDT 24
Peak memory 222940 kb
Host smart-40ffe502-b814-4b5a-91cf-3d4ecb98fab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002632981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.3002632981 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_key_error/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.3292711225
Short name T96
Test name
Test status
Simulation time 45516616 ps
CPU time 1.21 seconds
Started Jul 25 04:42:24 PM PDT 24
Finished Jul 25 04:42:26 PM PDT 24
Peak memory 216424 kb
Host smart-25ad52d2-8d57-4ed5-91be-c657d4449b7b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292711225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_
errors.3292711225 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/default/24.kmac_lc_escalation.1251566068
Short name T59
Test name
Test status
Simulation time 133452878 ps
CPU time 1.36 seconds
Started Jul 25 05:14:47 PM PDT 24
Finished Jul 25 05:14:48 PM PDT 24
Peak memory 226620 kb
Host smart-c971ec08-86ce-4a62-b4c8-be60e3cd6d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251566068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.1251566068 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/24.kmac_lc_escalation/latest

Test location /workspace/coverage/default/1.kmac_edn_timeout_error.948874609
Short name T78
Test name
Test status
Simulation time 144603967 ps
CPU time 1.33 seconds
Started Jul 25 05:11:59 PM PDT 24
Finished Jul 25 05:12:00 PM PDT 24
Peak memory 218372 kb
Host smart-ed32295e-1d7a-489d-b45a-c11283fe3114
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=948874609 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.948874609 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_ready_error.3651461472
Short name T11
Test name
Test status
Simulation time 596239445 ps
CPU time 7.35 seconds
Started Jul 25 05:11:58 PM PDT 24
Finished Jul 25 05:12:06 PM PDT 24
Peak memory 218440 kb
Host smart-c886f99f-d3c7-41d8-8603-c113d9d3e41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651461472 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.3651461472 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_ready_error/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_intr_test.2269169809
Short name T137
Test name
Test status
Simulation time 21453504 ps
CPU time 0.83 seconds
Started Jul 25 04:42:41 PM PDT 24
Finished Jul 25 04:42:42 PM PDT 24
Peak memory 215780 kb
Host smart-08dbdca2-9c09-47ac-a294-211132c2e0d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269169809 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.2269169809 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_intr_test/latest

Test location /workspace/coverage/default/13.kmac_stress_all.4150927126
Short name T76
Test name
Test status
Simulation time 142645303027 ps
CPU time 2109.7 seconds
Started Jul 25 05:13:13 PM PDT 24
Finished Jul 25 05:48:23 PM PDT 24
Peak memory 405432 kb
Host smart-9d04355e-0fc1-4580-9b74-c19f2d24d47f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4150927126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.4150927126 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_stress_all/latest

Test location /workspace/coverage/default/14.kmac_lc_escalation.420817610
Short name T650
Test name
Test status
Simulation time 159068718 ps
CPU time 1.45 seconds
Started Jul 25 05:13:26 PM PDT 24
Finished Jul 25 05:13:27 PM PDT 24
Peak memory 226616 kb
Host smart-25d97f09-bc0b-4e1d-b1d7-4f22c3a7400f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420817610 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.420817610 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/14.kmac_lc_escalation/latest

Test location /workspace/coverage/default/17.kmac_lc_escalation.811957105
Short name T45
Test name
Test status
Simulation time 321395560 ps
CPU time 7.69 seconds
Started Jul 25 05:13:50 PM PDT 24
Finished Jul 25 05:13:58 PM PDT 24
Peak memory 226708 kb
Host smart-58e3d80c-681a-4b10-93a5-e08ee42d9ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811957105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.811957105 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/17.kmac_lc_escalation/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.1786643976
Short name T92
Test name
Test status
Simulation time 74121173 ps
CPU time 1.95 seconds
Started Jul 25 04:42:24 PM PDT 24
Finished Jul 25 04:42:31 PM PDT 24
Peak memory 218504 kb
Host smart-8b744bf6-16d9-4d91-b7c7-fbe0b1481702
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786643976 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac
_shadow_reg_errors_with_csr_rw.1786643976 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.kmac_entropy_mode_error.3379923674
Short name T872
Test name
Test status
Simulation time 241496050 ps
CPU time 1.09 seconds
Started Jul 25 05:11:51 PM PDT 24
Finished Jul 25 05:11:52 PM PDT 24
Peak memory 222040 kb
Host smart-89a7e1e4-fb51-4ec5-acae-4434fcba5500
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3379923674 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.3379923674 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/9.kmac_lc_escalation.775538176
Short name T75
Test name
Test status
Simulation time 49614004 ps
CPU time 1.48 seconds
Started Jul 25 05:12:50 PM PDT 24
Finished Jul 25 05:12:51 PM PDT 24
Peak memory 226588 kb
Host smart-4add7874-8e9b-4761-bfd5-ef634466d894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775538176 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.775538176 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_lc_escalation/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_shake_128.1518447355
Short name T52
Test name
Test status
Simulation time 266854017097 ps
CPU time 6182.65 seconds
Started Jul 25 05:20:36 PM PDT 24
Finished Jul 25 07:03:39 PM PDT 24
Peak memory 659556 kb
Host smart-a9fd0269-8126-4b74-a9cf-20fe970ff926
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1518447355 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_128.1518447355 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.148339112
Short name T154
Test name
Test status
Simulation time 51710522 ps
CPU time 1.16 seconds
Started Jul 25 04:42:25 PM PDT 24
Finished Jul 25 04:42:31 PM PDT 24
Peak memory 215800 kb
Host smart-341ab665-d768-4274-ba24-82dbb464f0e0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148339112 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partial
_access.148339112 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_mem_partial_access/latest

Test location /workspace/coverage/default/13.kmac_alert_test.2057344694
Short name T114
Test name
Test status
Simulation time 17210573 ps
CPU time 0.87 seconds
Started Jul 25 05:13:25 PM PDT 24
Finished Jul 25 05:13:26 PM PDT 24
Peak memory 218260 kb
Host smart-3bc529a6-e311-4771-8613-915a44768b15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057344694 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.2057344694 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_alert_test/latest

Test location /workspace/coverage/default/0.kmac_lc_escalation.634065466
Short name T881
Test name
Test status
Simulation time 71738865 ps
CPU time 1.32 seconds
Started Jul 25 05:11:51 PM PDT 24
Finished Jul 25 05:11:52 PM PDT 24
Peak memory 226624 kb
Host smart-23dc167a-4402-4449-a9ce-cfed6b8e72e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634065466 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.634065466 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_lc_escalation/latest

Test location /workspace/coverage/default/10.kmac_lc_escalation.1317389673
Short name T57
Test name
Test status
Simulation time 140204567 ps
CPU time 1.47 seconds
Started Jul 25 05:13:00 PM PDT 24
Finished Jul 25 05:13:02 PM PDT 24
Peak memory 226600 kb
Host smart-387effe8-76e5-49b6-98de-aa9d50433e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317389673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.1317389673 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/10.kmac_lc_escalation/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.2822042485
Short name T89
Test name
Test status
Simulation time 36674246 ps
CPU time 1.11 seconds
Started Jul 25 04:42:31 PM PDT 24
Finished Jul 25 04:42:32 PM PDT 24
Peak memory 216120 kb
Host smart-3fa80da7-5b52-43d8-a82b-315cb947cd79
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822042485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg
_errors.2822042485 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_intr_test.103552891
Short name T170
Test name
Test status
Simulation time 74128214 ps
CPU time 0.87 seconds
Started Jul 25 04:42:51 PM PDT 24
Finished Jul 25 04:42:52 PM PDT 24
Peak memory 215848 kb
Host smart-60155580-d760-46ca-a38a-a18d5525b5da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103552891 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.103552891 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/11.kmac_intr_test/latest

Test location /workspace/coverage/default/0.kmac_sec_cm.1270885119
Short name T32
Test name
Test status
Simulation time 11585100232 ps
CPU time 39.73 seconds
Started Jul 25 05:11:58 PM PDT 24
Finished Jul 25 05:12:38 PM PDT 24
Peak memory 246432 kb
Host smart-6e5d6155-62b1-4fec-a7a9-52022042862f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270885119 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.1270885119 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/0.kmac_sec_cm/latest

Test location /workspace/coverage/default/3.kmac_stress_all.2173974205
Short name T64
Test name
Test status
Simulation time 6975141078 ps
CPU time 117.08 seconds
Started Jul 25 05:12:17 PM PDT 24
Finished Jul 25 05:14:15 PM PDT 24
Peak memory 251448 kb
Host smart-d7395c1c-5615-45e8-8360-fabdc5f8dde8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2173974205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.2173974205 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_stress_all/latest

Test location /workspace/coverage/default/29.kmac_key_error.1163790438
Short name T101
Test name
Test status
Simulation time 1390331777 ps
CPU time 10.26 seconds
Started Jul 25 05:15:35 PM PDT 24
Finished Jul 25 05:15:45 PM PDT 24
Peak memory 224732 kb
Host smart-02e54f82-6737-4989-92a4-caef89d7c701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163790438 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.1163790438 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_key_error/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_intr_test.3361524857
Short name T1113
Test name
Test status
Simulation time 43795662 ps
CPU time 0.75 seconds
Started Jul 25 04:42:36 PM PDT 24
Finished Jul 25 04:42:37 PM PDT 24
Peak memory 215772 kb
Host smart-cd293362-adf8-4c95-82c3-0426d16db354
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361524857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.3361524857 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.504783251
Short name T189
Test name
Test status
Simulation time 189012948 ps
CPU time 4.46 seconds
Started Jul 25 04:42:49 PM PDT 24
Finished Jul 25 04:42:53 PM PDT 24
Peak memory 215832 kb
Host smart-16be9562-5a29-4460-8041-82f8a6230814
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504783251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.50478
3251 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/3.kmac_app_with_partial_data.4254974241
Short name T182
Test name
Test status
Simulation time 31576921099 ps
CPU time 374.34 seconds
Started Jul 25 05:12:12 PM PDT 24
Finished Jul 25 05:18:27 PM PDT 24
Peak memory 250068 kb
Host smart-e1a44191-af19-4cb5-a932-8f581d37db57
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254974241 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_par
tial_data.4254974241 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_app_with_partial_data/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.663332892
Short name T192
Test name
Test status
Simulation time 61132182 ps
CPU time 2.59 seconds
Started Jul 25 04:42:34 PM PDT 24
Finished Jul 25 04:42:38 PM PDT 24
Peak memory 215136 kb
Host smart-344718d5-1916-486d-9ea9-f3667ac39aea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663332892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.663332
892 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.710008254
Short name T187
Test name
Test status
Simulation time 196884053 ps
CPU time 4.84 seconds
Started Jul 25 04:42:53 PM PDT 24
Finished Jul 25 04:42:59 PM PDT 24
Peak memory 215868 kb
Host smart-4cfe803c-8da4-4095-8a54-6553fdfae81d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710008254 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.71000
8254 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/28.kmac_stress_all.310298057
Short name T458
Test name
Test status
Simulation time 64138196880 ps
CPU time 439.75 seconds
Started Jul 25 05:15:24 PM PDT 24
Finished Jul 25 05:22:44 PM PDT 24
Peak memory 272964 kb
Host smart-c3416684-d338-4c3c-945a-f1bbae6b0af5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=310298057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.310298057 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.2317624876
Short name T1209
Test name
Test status
Simulation time 140575080 ps
CPU time 4.29 seconds
Started Jul 25 04:42:24 PM PDT 24
Finished Jul 25 04:42:28 PM PDT 24
Peak memory 215832 kb
Host smart-b6809d13-f4aa-4f6d-8790-f3acbc45614b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317624876 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.2317624
876 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.1969964626
Short name T1222
Test name
Test status
Simulation time 515695957 ps
CPU time 9.31 seconds
Started Jul 25 04:42:54 PM PDT 24
Finished Jul 25 04:43:04 PM PDT 24
Peak memory 215792 kb
Host smart-4a2939ef-5598-4763-8b48-fa26b7d18b01
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969964626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.1969964
626 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.1896475172
Short name T172
Test name
Test status
Simulation time 199624153 ps
CPU time 1.23 seconds
Started Jul 25 04:42:42 PM PDT 24
Finished Jul 25 04:42:44 PM PDT 24
Peak memory 215872 kb
Host smart-97cda6d1-a914-41ca-bc99-30292ef3d095
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896475172 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.1896475
172 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.4211816096
Short name T1091
Test name
Test status
Simulation time 49037530 ps
CPU time 1.81 seconds
Started Jul 25 04:42:25 PM PDT 24
Finished Jul 25 04:42:27 PM PDT 24
Peak memory 220080 kb
Host smart-157cbaf2-540f-41e0-be7a-41c62913e508
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211816096 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.kmac_csr_mem_rw_with_rand_reset.4211816096 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_rw.521306959
Short name T1104
Test name
Test status
Simulation time 12963043 ps
CPU time 0.98 seconds
Started Jul 25 04:42:11 PM PDT 24
Finished Jul 25 04:42:13 PM PDT 24
Peak memory 215056 kb
Host smart-8b0c29f3-6a60-4879-9965-eb4fec49f0a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521306959 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.521306959 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_intr_test.1312042028
Short name T176
Test name
Test status
Simulation time 32755623 ps
CPU time 0.8 seconds
Started Jul 25 04:42:53 PM PDT 24
Finished Jul 25 04:42:54 PM PDT 24
Peak memory 215840 kb
Host smart-66512c5e-11eb-49f0-9611-81b1734519f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312042028 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.1312042028 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_walk.2274110947
Short name T1107
Test name
Test status
Simulation time 11962495 ps
CPU time 0.75 seconds
Started Jul 25 04:42:11 PM PDT 24
Finished Jul 25 04:42:12 PM PDT 24
Peak memory 215844 kb
Host smart-621e71f8-f091-43c5-a20a-3e7db8a78205
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274110947 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.2274110947
+enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.3155205815
Short name T1141
Test name
Test status
Simulation time 226059614 ps
CPU time 1.72 seconds
Started Jul 25 04:42:12 PM PDT 24
Finished Jul 25 04:42:14 PM PDT 24
Peak memory 215824 kb
Host smart-3caa2553-a5a1-4a53-b95b-3d2f964352a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155205815 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr
_outstanding.3155205815 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.3129752676
Short name T95
Test name
Test status
Simulation time 17224457 ps
CPU time 0.81 seconds
Started Jul 25 04:42:09 PM PDT 24
Finished Jul 25 04:42:10 PM PDT 24
Peak memory 215812 kb
Host smart-949ecd17-62eb-46b5-baf6-333ed27747d7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129752676 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_
errors.3129752676 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_errors.937991241
Short name T1164
Test name
Test status
Simulation time 135520089 ps
CPU time 2.29 seconds
Started Jul 25 04:42:19 PM PDT 24
Finished Jul 25 04:42:22 PM PDT 24
Peak memory 214916 kb
Host smart-d385d349-a26b-4563-ad2b-bd396444d2be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937991241 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.937991241 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/0.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.226271813
Short name T1078
Test name
Test status
Simulation time 405059337 ps
CPU time 4.87 seconds
Started Jul 25 04:42:25 PM PDT 24
Finished Jul 25 04:42:30 PM PDT 24
Peak memory 215788 kb
Host smart-7c1d3fef-29d6-477b-9126-b5c020ac6c8c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226271813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.22627181
3 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.3225517815
Short name T1137
Test name
Test status
Simulation time 148821622 ps
CPU time 7.87 seconds
Started Jul 25 04:42:29 PM PDT 24
Finished Jul 25 04:42:37 PM PDT 24
Peak memory 215820 kb
Host smart-f5c2d642-5be0-4263-8764-9c0429e1a396
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225517815 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.3225517
815 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.2653681166
Short name T1151
Test name
Test status
Simulation time 28989115 ps
CPU time 0.98 seconds
Started Jul 25 04:42:13 PM PDT 24
Finished Jul 25 04:42:14 PM PDT 24
Peak memory 215788 kb
Host smart-acf942b2-7ac8-44e5-900b-d88effae3e77
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653681166 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.2653681
166 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.2394180315
Short name T1101
Test name
Test status
Simulation time 78147275 ps
CPU time 1.61 seconds
Started Jul 25 04:42:47 PM PDT 24
Finished Jul 25 04:42:49 PM PDT 24
Peak memory 216936 kb
Host smart-0ef0129b-aff2-44b4-810f-a4c2b260b6e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394180315 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.kmac_csr_mem_rw_with_rand_reset.2394180315 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_rw.3964714363
Short name T1177
Test name
Test status
Simulation time 100455397 ps
CPU time 1.16 seconds
Started Jul 25 04:42:54 PM PDT 24
Finished Jul 25 04:42:55 PM PDT 24
Peak memory 215948 kb
Host smart-d757df6b-5cb1-4535-a2d0-ae826d6c3eb2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964714363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.3964714363 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_intr_test.826520745
Short name T180
Test name
Test status
Simulation time 27128157 ps
CPU time 0.8 seconds
Started Jul 25 04:42:14 PM PDT 24
Finished Jul 25 04:42:20 PM PDT 24
Peak memory 215796 kb
Host smart-46d9f26a-6d02-4667-a41c-a70c2d03303d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826520745 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.826520745 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/1.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.51823368
Short name T155
Test name
Test status
Simulation time 106440027 ps
CPU time 1.26 seconds
Started Jul 25 04:42:19 PM PDT 24
Finished Jul 25 04:42:21 PM PDT 24
Peak memory 214712 kb
Host smart-769fd697-eaef-4a4d-bb97-dbde647c2a1d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51823368 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partial_
access.51823368 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_walk.1018132909
Short name T1221
Test name
Test status
Simulation time 16438814 ps
CPU time 0.79 seconds
Started Jul 25 04:42:14 PM PDT 24
Finished Jul 25 04:42:15 PM PDT 24
Peak memory 216088 kb
Host smart-fd070991-9a1f-4b96-a531-76f5295fd4bd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018132909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.1018132909
+enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.4036407039
Short name T1130
Test name
Test status
Simulation time 91105346 ps
CPU time 1.5 seconds
Started Jul 25 04:42:17 PM PDT 24
Finished Jul 25 04:42:18 PM PDT 24
Peak memory 215888 kb
Host smart-254f126c-53e4-41f2-ac65-877358042ed7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036407039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr
_outstanding.4036407039 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.1073427619
Short name T1228
Test name
Test status
Simulation time 38668422 ps
CPU time 1.45 seconds
Started Jul 25 04:42:41 PM PDT 24
Finished Jul 25 04:42:43 PM PDT 24
Peak memory 217212 kb
Host smart-002ecf84-2181-4ca8-96a0-672a2e374d9b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073427619 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_
errors.1073427619 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.3460371555
Short name T131
Test name
Test status
Simulation time 26822617 ps
CPU time 1.43 seconds
Started Jul 25 04:42:40 PM PDT 24
Finished Jul 25 04:42:42 PM PDT 24
Peak memory 215884 kb
Host smart-85a1e999-9b8a-4d1b-b54d-dc87fb08aa85
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460371555 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac
_shadow_reg_errors_with_csr_rw.3460371555 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_errors.3952492081
Short name T1145
Test name
Test status
Simulation time 375493620 ps
CPU time 2.91 seconds
Started Jul 25 04:42:13 PM PDT 24
Finished Jul 25 04:42:16 PM PDT 24
Peak memory 215912 kb
Host smart-5a062a30-554d-436e-a92c-a4a32257a053
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952492081 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.3952492081 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.1692311234
Short name T190
Test name
Test status
Simulation time 272471252 ps
CPU time 3.98 seconds
Started Jul 25 04:42:12 PM PDT 24
Finished Jul 25 04:42:17 PM PDT 24
Peak memory 215828 kb
Host smart-219680b6-caa3-4385-9731-df17d3134646
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692311234 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.16923
11234 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.4107443809
Short name T1110
Test name
Test status
Simulation time 75352155 ps
CPU time 2.48 seconds
Started Jul 25 04:42:52 PM PDT 24
Finished Jul 25 04:42:55 PM PDT 24
Peak memory 220516 kb
Host smart-2de4c0ef-d2a4-4d30-a501-0f9f31584106
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107443809 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.kmac_csr_mem_rw_with_rand_reset.4107443809 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_rw.3744208564
Short name T199
Test name
Test status
Simulation time 62080304 ps
CPU time 0.95 seconds
Started Jul 25 04:42:42 PM PDT 24
Finished Jul 25 04:42:43 PM PDT 24
Peak memory 215744 kb
Host smart-427e7259-f22c-43ef-8c82-2eb56beb714c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744208564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.3744208564 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.4280664819
Short name T1174
Test name
Test status
Simulation time 60862174 ps
CPU time 1.73 seconds
Started Jul 25 04:42:15 PM PDT 24
Finished Jul 25 04:42:17 PM PDT 24
Peak memory 215804 kb
Host smart-131b6743-68f1-47bd-aa3b-ec4ec4431120
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280664819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_cs
r_outstanding.4280664819 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.880826641
Short name T1126
Test name
Test status
Simulation time 28737333 ps
CPU time 0.81 seconds
Started Jul 25 04:42:32 PM PDT 24
Finished Jul 25 04:42:33 PM PDT 24
Peak memory 215796 kb
Host smart-e82f4394-a7cb-400e-ae33-054bd7647bd7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880826641 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_
errors.880826641 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.2109340999
Short name T93
Test name
Test status
Simulation time 57974903 ps
CPU time 2.67 seconds
Started Jul 25 04:42:42 PM PDT 24
Finished Jul 25 04:42:44 PM PDT 24
Peak memory 218756 kb
Host smart-92d681c1-1c95-4bed-8559-c97e304b689b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109340999 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kma
c_shadow_reg_errors_with_csr_rw.2109340999 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_errors.3764233605
Short name T142
Test name
Test status
Simulation time 400032582 ps
CPU time 2.93 seconds
Started Jul 25 04:42:35 PM PDT 24
Finished Jul 25 04:42:43 PM PDT 24
Peak memory 215968 kb
Host smart-6061f95f-1f14-4b39-800b-c96e806f7a15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764233605 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.3764233605 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.506191227
Short name T1186
Test name
Test status
Simulation time 183714370 ps
CPU time 1.59 seconds
Started Jul 25 04:42:16 PM PDT 24
Finished Jul 25 04:42:18 PM PDT 24
Peak memory 216944 kb
Host smart-9f9f9550-04d9-4753-bfb5-93edc80a0cc7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506191227 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.kmac_csr_mem_rw_with_rand_reset.506191227 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_rw.3651038943
Short name T1224
Test name
Test status
Simulation time 61785929 ps
CPU time 0.96 seconds
Started Jul 25 04:42:23 PM PDT 24
Finished Jul 25 04:42:24 PM PDT 24
Peak memory 215688 kb
Host smart-3384c2d8-f29f-45be-bf67-9b137d012d48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651038943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.3651038943 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.1481327662
Short name T1092
Test name
Test status
Simulation time 61767418 ps
CPU time 1.71 seconds
Started Jul 25 04:42:48 PM PDT 24
Finished Jul 25 04:42:50 PM PDT 24
Peak memory 215884 kb
Host smart-cff5feef-1054-4cbb-bb58-8986e022c4ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481327662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_cs
r_outstanding.1481327662 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.2416798040
Short name T1131
Test name
Test status
Simulation time 62961349 ps
CPU time 1.09 seconds
Started Jul 25 04:42:44 PM PDT 24
Finished Jul 25 04:42:45 PM PDT 24
Peak memory 216080 kb
Host smart-73979195-49b1-4793-8410-67e9defa8947
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416798040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg
_errors.2416798040 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.4216173977
Short name T1156
Test name
Test status
Simulation time 268884963 ps
CPU time 1.96 seconds
Started Jul 25 04:42:48 PM PDT 24
Finished Jul 25 04:42:51 PM PDT 24
Peak memory 218668 kb
Host smart-83df376d-109a-4f7e-870d-b3b97bfe0978
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216173977 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kma
c_shadow_reg_errors_with_csr_rw.4216173977 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_errors.2356139686
Short name T1179
Test name
Test status
Simulation time 150155284 ps
CPU time 2.61 seconds
Started Jul 25 04:42:43 PM PDT 24
Finished Jul 25 04:42:46 PM PDT 24
Peak memory 216012 kb
Host smart-f7c6f53d-bace-4a74-b923-6fd43c12d747
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356139686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.2356139686 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.3352696446
Short name T196
Test name
Test status
Simulation time 247160610 ps
CPU time 3.03 seconds
Started Jul 25 04:42:27 PM PDT 24
Finished Jul 25 04:42:30 PM PDT 24
Peak memory 215780 kb
Host smart-ca0e101f-d650-4097-a2bc-0fc49f964838
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352696446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.3352
696446 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.1265634766
Short name T1204
Test name
Test status
Simulation time 24861647 ps
CPU time 1.64 seconds
Started Jul 25 04:42:43 PM PDT 24
Finished Jul 25 04:42:45 PM PDT 24
Peak memory 220464 kb
Host smart-42ff7590-e50b-4b84-a0d6-c3842beb45f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265634766 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.kmac_csr_mem_rw_with_rand_reset.1265634766 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_rw.1836566786
Short name T1160
Test name
Test status
Simulation time 59722389 ps
CPU time 1.09 seconds
Started Jul 25 04:42:32 PM PDT 24
Finished Jul 25 04:42:38 PM PDT 24
Peak memory 215760 kb
Host smart-dd8f2558-539d-4071-9fa0-99a51409541e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836566786 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.1836566786 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.53692101
Short name T1159
Test name
Test status
Simulation time 270965409 ps
CPU time 1.82 seconds
Started Jul 25 04:42:45 PM PDT 24
Finished Jul 25 04:42:47 PM PDT 24
Peak memory 215892 kb
Host smart-d516d396-6555-4fe2-92f9-a9b5dc5c9d7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53692101 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_csr_
outstanding.53692101 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.1717630821
Short name T91
Test name
Test status
Simulation time 63400070 ps
CPU time 1.28 seconds
Started Jul 25 04:42:54 PM PDT 24
Finished Jul 25 04:42:55 PM PDT 24
Peak memory 216104 kb
Host smart-e11d8937-3905-478d-9b5b-233a44d4e1ce
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717630821 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg
_errors.1717630821 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.1054397849
Short name T1125
Test name
Test status
Simulation time 71240792 ps
CPU time 1.86 seconds
Started Jul 25 04:42:21 PM PDT 24
Finished Jul 25 04:42:23 PM PDT 24
Peak memory 218528 kb
Host smart-eca921d9-3101-4662-bf01-b82699b2adbd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054397849 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kma
c_shadow_reg_errors_with_csr_rw.1054397849 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_errors.1057845157
Short name T1197
Test name
Test status
Simulation time 126038236 ps
CPU time 3.1 seconds
Started Jul 25 04:42:47 PM PDT 24
Finished Jul 25 04:42:50 PM PDT 24
Peak memory 215924 kb
Host smart-b099b7e6-d7ac-45ae-b84e-1984a9cdc436
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057845157 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.1057845157 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.2662541159
Short name T164
Test name
Test status
Simulation time 394387998 ps
CPU time 2.51 seconds
Started Jul 25 04:42:44 PM PDT 24
Finished Jul 25 04:42:47 PM PDT 24
Peak memory 220744 kb
Host smart-d21d006d-507f-4f69-8950-cb8e6b0fda53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662541159 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.kmac_csr_mem_rw_with_rand_reset.2662541159 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_rw.1769870948
Short name T1201
Test name
Test status
Simulation time 175232895 ps
CPU time 1.14 seconds
Started Jul 25 04:42:35 PM PDT 24
Finished Jul 25 04:42:36 PM PDT 24
Peak memory 215888 kb
Host smart-fa077f73-a8ac-493b-b5e7-55a302a9224b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769870948 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.1769870948 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_intr_test.3036090732
Short name T1178
Test name
Test status
Simulation time 100213054 ps
CPU time 0.81 seconds
Started Jul 25 04:42:53 PM PDT 24
Finished Jul 25 04:42:54 PM PDT 24
Peak memory 215820 kb
Host smart-30c6c020-91d9-4de1-8896-83873804bfc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036090732 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.3036090732 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.1839580710
Short name T173
Test name
Test status
Simulation time 53653201 ps
CPU time 1.57 seconds
Started Jul 25 04:42:41 PM PDT 24
Finished Jul 25 04:42:43 PM PDT 24
Peak memory 215916 kb
Host smart-77378a02-9966-45eb-9cbc-02d2c8a76a07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839580710 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_cs
r_outstanding.1839580710 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.601044992
Short name T1203
Test name
Test status
Simulation time 196112032 ps
CPU time 2.45 seconds
Started Jul 25 04:42:45 PM PDT 24
Finished Jul 25 04:42:48 PM PDT 24
Peak memory 218916 kb
Host smart-bbb9a775-dc5d-46b9-b9ff-d92d20a46519
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601044992 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac
_shadow_reg_errors_with_csr_rw.601044992 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_errors.640624108
Short name T1148
Test name
Test status
Simulation time 294441369 ps
CPU time 3.13 seconds
Started Jul 25 04:42:45 PM PDT 24
Finished Jul 25 04:42:48 PM PDT 24
Peak memory 215940 kb
Host smart-c30f578e-5f49-46db-81f3-3858be4cc7df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640624108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.640624108 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/13.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.1901699834
Short name T188
Test name
Test status
Simulation time 188800839 ps
CPU time 2.58 seconds
Started Jul 25 04:42:35 PM PDT 24
Finished Jul 25 04:42:38 PM PDT 24
Peak memory 215872 kb
Host smart-bc1f4554-c170-4c83-86fe-e56d47adfb8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901699834 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.1901
699834 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.276582272
Short name T139
Test name
Test status
Simulation time 160407235 ps
CPU time 1.47 seconds
Started Jul 25 04:42:40 PM PDT 24
Finished Jul 25 04:42:41 PM PDT 24
Peak memory 218768 kb
Host smart-091475c0-699d-489d-a667-84a1fbd112bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276582272 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.kmac_csr_mem_rw_with_rand_reset.276582272 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_rw.4266891599
Short name T1162
Test name
Test status
Simulation time 32141612 ps
CPU time 1.14 seconds
Started Jul 25 04:42:54 PM PDT 24
Finished Jul 25 04:42:56 PM PDT 24
Peak memory 215940 kb
Host smart-800427ed-c85a-4d7d-b02f-f433634efcaf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266891599 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.4266891599 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_intr_test.1362707775
Short name T1123
Test name
Test status
Simulation time 60804893 ps
CPU time 0.8 seconds
Started Jul 25 04:42:49 PM PDT 24
Finished Jul 25 04:42:50 PM PDT 24
Peak memory 215840 kb
Host smart-60ef5161-164b-4afe-ab3e-33c5189fe919
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362707775 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.1362707775 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.249704574
Short name T1082
Test name
Test status
Simulation time 886597694 ps
CPU time 2.96 seconds
Started Jul 25 04:42:37 PM PDT 24
Finished Jul 25 04:42:41 PM PDT 24
Peak memory 215944 kb
Host smart-10e16173-12c3-4163-bc51-a6fda64c9d36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249704574 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_csr
_outstanding.249704574 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.86107846
Short name T1194
Test name
Test status
Simulation time 40419695 ps
CPU time 1.17 seconds
Started Jul 25 04:42:43 PM PDT 24
Finished Jul 25 04:42:44 PM PDT 24
Peak memory 216220 kb
Host smart-5890d1f8-b076-4c11-a39d-9bc65bb15f45
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86107846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_e
rrors.86107846 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.513274429
Short name T1093
Test name
Test status
Simulation time 23050829 ps
CPU time 1.39 seconds
Started Jul 25 04:42:53 PM PDT 24
Finished Jul 25 04:42:54 PM PDT 24
Peak memory 215980 kb
Host smart-441b09e9-6bca-415f-90e1-4d28f10b57fb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513274429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac
_shadow_reg_errors_with_csr_rw.513274429 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_errors.2230544453
Short name T140
Test name
Test status
Simulation time 164549007 ps
CPU time 2.32 seconds
Started Jul 25 04:42:53 PM PDT 24
Finished Jul 25 04:42:55 PM PDT 24
Peak memory 215964 kb
Host smart-b97559e8-f3ff-4edf-a2be-a17cf40593ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230544453 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.2230544453 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.3230935806
Short name T195
Test name
Test status
Simulation time 175014201 ps
CPU time 3.98 seconds
Started Jul 25 04:42:20 PM PDT 24
Finished Jul 25 04:42:24 PM PDT 24
Peak memory 215656 kb
Host smart-c8813155-a17a-4e20-8119-549cae288001
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230935806 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.3230
935806 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.3590552821
Short name T152
Test name
Test status
Simulation time 24096373 ps
CPU time 1.8 seconds
Started Jul 25 04:42:47 PM PDT 24
Finished Jul 25 04:42:49 PM PDT 24
Peak memory 220772 kb
Host smart-36e49f35-317f-410f-a55d-e39145b150dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590552821 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.kmac_csr_mem_rw_with_rand_reset.3590552821 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_rw.3720504443
Short name T160
Test name
Test status
Simulation time 151981991 ps
CPU time 1.14 seconds
Started Jul 25 04:42:38 PM PDT 24
Finished Jul 25 04:42:39 PM PDT 24
Peak memory 215892 kb
Host smart-7bffd47f-14d0-4d34-a0a0-75b781121150
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720504443 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.3720504443 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_intr_test.3815665812
Short name T1103
Test name
Test status
Simulation time 15529878 ps
CPU time 0.81 seconds
Started Jul 25 04:42:25 PM PDT 24
Finished Jul 25 04:42:26 PM PDT 24
Peak memory 215772 kb
Host smart-d46770b9-d44b-479e-921a-4c38ba457bb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815665812 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.3815665812 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.14533664
Short name T1142
Test name
Test status
Simulation time 369718711 ps
CPU time 1.79 seconds
Started Jul 25 04:42:48 PM PDT 24
Finished Jul 25 04:42:50 PM PDT 24
Peak memory 215892 kb
Host smart-c0057d79-8ebc-4902-9535-9141eb55ec5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14533664 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_csr_
outstanding.14533664 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.4167550053
Short name T1118
Test name
Test status
Simulation time 19062181 ps
CPU time 0.93 seconds
Started Jul 25 04:42:36 PM PDT 24
Finished Jul 25 04:42:37 PM PDT 24
Peak memory 215792 kb
Host smart-a6eda90a-808c-44ce-80e2-bf3c8ca47d6c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167550053 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg
_errors.4167550053 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.115735667
Short name T1191
Test name
Test status
Simulation time 28163719 ps
CPU time 1.56 seconds
Started Jul 25 04:42:40 PM PDT 24
Finished Jul 25 04:42:41 PM PDT 24
Peak memory 218292 kb
Host smart-2eaef653-73a3-4be3-b440-be172164a514
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115735667 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac
_shadow_reg_errors_with_csr_rw.115735667 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_errors.3902180460
Short name T1089
Test name
Test status
Simulation time 22222390 ps
CPU time 1.31 seconds
Started Jul 25 04:42:28 PM PDT 24
Finished Jul 25 04:42:29 PM PDT 24
Peak memory 215904 kb
Host smart-bf7a3635-dc85-48b9-a917-5a81a82a5d54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902180460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.3902180460 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.3276888998
Short name T134
Test name
Test status
Simulation time 669042245 ps
CPU time 2.71 seconds
Started Jul 25 04:42:38 PM PDT 24
Finished Jul 25 04:42:41 PM PDT 24
Peak memory 215816 kb
Host smart-bdc795f1-a3cb-4f6a-91c6-33b0945562b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276888998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.3276
888998 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.3648936349
Short name T1163
Test name
Test status
Simulation time 44338489 ps
CPU time 2.02 seconds
Started Jul 25 04:42:58 PM PDT 24
Finished Jul 25 04:43:00 PM PDT 24
Peak memory 220348 kb
Host smart-324aa3c4-8c58-492d-b6a5-9c43feba6073
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648936349 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.kmac_csr_mem_rw_with_rand_reset.3648936349 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_rw.3666721540
Short name T1112
Test name
Test status
Simulation time 32195885 ps
CPU time 0.94 seconds
Started Jul 25 04:43:00 PM PDT 24
Finished Jul 25 04:43:01 PM PDT 24
Peak memory 215756 kb
Host smart-528c5852-a87c-42f5-886e-c0b95d46048e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666721540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.3666721540 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_intr_test.431356461
Short name T1100
Test name
Test status
Simulation time 28935163 ps
CPU time 0.78 seconds
Started Jul 25 04:42:43 PM PDT 24
Finished Jul 25 04:42:44 PM PDT 24
Peak memory 215804 kb
Host smart-e540ffea-db7d-44c4-929f-c3403ea1f855
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431356461 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.431356461 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/16.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.2723857108
Short name T1172
Test name
Test status
Simulation time 290658776 ps
CPU time 2.23 seconds
Started Jul 25 04:42:35 PM PDT 24
Finished Jul 25 04:42:38 PM PDT 24
Peak memory 215896 kb
Host smart-a1dbe8fb-9d95-49a8-8495-f268ad35788d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723857108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_cs
r_outstanding.2723857108 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.2845505941
Short name T1220
Test name
Test status
Simulation time 54831553 ps
CPU time 1.06 seconds
Started Jul 25 04:42:26 PM PDT 24
Finished Jul 25 04:42:27 PM PDT 24
Peak memory 217188 kb
Host smart-fb11d6fe-4af8-4a8d-96bb-cb37d9f50cea
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845505941 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg
_errors.2845505941 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.2319356053
Short name T1216
Test name
Test status
Simulation time 65694777 ps
CPU time 2.46 seconds
Started Jul 25 04:42:42 PM PDT 24
Finished Jul 25 04:42:45 PM PDT 24
Peak memory 219692 kb
Host smart-bcd531a1-67c4-4595-bf12-5bb6dc17dc97
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319356053 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kma
c_shadow_reg_errors_with_csr_rw.2319356053 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_errors.609335259
Short name T1150
Test name
Test status
Simulation time 52035930 ps
CPU time 1.62 seconds
Started Jul 25 04:42:48 PM PDT 24
Finished Jul 25 04:42:50 PM PDT 24
Peak memory 215600 kb
Host smart-abeeef8e-0bf2-43ed-9df9-804ce623d30b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609335259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.609335259 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/16.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.1965966225
Short name T1208
Test name
Test status
Simulation time 853348280 ps
CPU time 4.8 seconds
Started Jul 25 04:42:53 PM PDT 24
Finished Jul 25 04:42:58 PM PDT 24
Peak memory 215892 kb
Host smart-67465003-0ba7-4aac-80d5-36ac1232e970
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965966225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.1965
966225 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.2232679654
Short name T138
Test name
Test status
Simulation time 83521120 ps
CPU time 1.66 seconds
Started Jul 25 04:42:53 PM PDT 24
Finished Jul 25 04:42:54 PM PDT 24
Peak memory 217120 kb
Host smart-43c58a9e-1536-4bbe-984f-096911d45ce7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232679654 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.kmac_csr_mem_rw_with_rand_reset.2232679654 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_rw.3127798845
Short name T198
Test name
Test status
Simulation time 38820074 ps
CPU time 0.91 seconds
Started Jul 25 04:43:01 PM PDT 24
Finished Jul 25 04:43:02 PM PDT 24
Peak memory 215772 kb
Host smart-eda658e4-dccc-45f9-a966-7f1789c02212
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127798845 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.3127798845 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_intr_test.1533780927
Short name T1169
Test name
Test status
Simulation time 16840190 ps
CPU time 0.88 seconds
Started Jul 25 04:42:38 PM PDT 24
Finished Jul 25 04:42:39 PM PDT 24
Peak memory 215776 kb
Host smart-b334eff0-9ed1-4178-9558-5ea6038648d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533780927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.1533780927 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.1390181534
Short name T1166
Test name
Test status
Simulation time 70508118 ps
CPU time 1.72 seconds
Started Jul 25 04:42:44 PM PDT 24
Finished Jul 25 04:42:46 PM PDT 24
Peak memory 215816 kb
Host smart-870afa84-2e54-4b9a-aebf-8985a95e1ed6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390181534 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_cs
r_outstanding.1390181534 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.1618493150
Short name T1192
Test name
Test status
Simulation time 76160246 ps
CPU time 1 seconds
Started Jul 25 04:42:47 PM PDT 24
Finished Jul 25 04:42:48 PM PDT 24
Peak memory 216040 kb
Host smart-f2bfb3ba-4371-49ed-b35c-8e9d896fc73a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618493150 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg
_errors.1618493150 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.1290698417
Short name T97
Test name
Test status
Simulation time 182592536 ps
CPU time 2.72 seconds
Started Jul 25 04:42:44 PM PDT 24
Finished Jul 25 04:42:47 PM PDT 24
Peak memory 219284 kb
Host smart-690e11c2-588e-438d-aa8e-e1e83cd5bc59
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290698417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kma
c_shadow_reg_errors_with_csr_rw.1290698417 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_errors.462540032
Short name T141
Test name
Test status
Simulation time 351648111 ps
CPU time 1.77 seconds
Started Jul 25 04:42:44 PM PDT 24
Finished Jul 25 04:42:45 PM PDT 24
Peak memory 215936 kb
Host smart-51e79d46-8e22-4d0a-8937-ef5a569863f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462540032 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.462540032 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/17.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.2869623783
Short name T1223
Test name
Test status
Simulation time 368746957 ps
CPU time 4.14 seconds
Started Jul 25 04:42:42 PM PDT 24
Finished Jul 25 04:42:46 PM PDT 24
Peak memory 215824 kb
Host smart-7df851f0-dc23-4755-aa55-970b8a98390d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869623783 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.2869
623783 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.1113828453
Short name T1195
Test name
Test status
Simulation time 60686761 ps
CPU time 1.47 seconds
Started Jul 25 04:43:05 PM PDT 24
Finished Jul 25 04:43:07 PM PDT 24
Peak memory 218392 kb
Host smart-b76394b4-01f4-42b9-afc1-c0b1f5c47dcf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113828453 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.kmac_csr_mem_rw_with_rand_reset.1113828453 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_rw.2553473840
Short name T165
Test name
Test status
Simulation time 38255757 ps
CPU time 1.19 seconds
Started Jul 25 04:42:44 PM PDT 24
Finished Jul 25 04:42:46 PM PDT 24
Peak memory 215884 kb
Host smart-918334a4-1d38-4ab2-8a57-fbce3e92b528
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553473840 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.2553473840 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_intr_test.291461290
Short name T181
Test name
Test status
Simulation time 64108737 ps
CPU time 0.85 seconds
Started Jul 25 04:42:45 PM PDT 24
Finished Jul 25 04:42:46 PM PDT 24
Peak memory 215808 kb
Host smart-b823156a-d066-4bf9-a831-4325d1091515
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291461290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.291461290 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/18.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.999204192
Short name T1184
Test name
Test status
Simulation time 100320010 ps
CPU time 1.72 seconds
Started Jul 25 04:42:53 PM PDT 24
Finished Jul 25 04:42:55 PM PDT 24
Peak memory 215612 kb
Host smart-d42927f8-a280-464c-90f9-e64fd9fae635
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999204192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_csr
_outstanding.999204192 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1261942921
Short name T90
Test name
Test status
Simulation time 26152426 ps
CPU time 0.97 seconds
Started Jul 25 04:42:35 PM PDT 24
Finished Jul 25 04:42:37 PM PDT 24
Peak memory 215800 kb
Host smart-5514327e-16d3-46b8-82c0-635b8a1b611a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261942921 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg
_errors.1261942921 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.78436361
Short name T1144
Test name
Test status
Simulation time 157367698 ps
CPU time 2.39 seconds
Started Jul 25 04:42:47 PM PDT 24
Finished Jul 25 04:42:49 PM PDT 24
Peak memory 215960 kb
Host smart-9601662a-f04c-4ef7-a671-a29d637359df
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78436361 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_
shadow_reg_errors_with_csr_rw.78436361 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_errors.107731865
Short name T1154
Test name
Test status
Simulation time 59760546 ps
CPU time 1.31 seconds
Started Jul 25 04:42:37 PM PDT 24
Finished Jul 25 04:42:38 PM PDT 24
Peak memory 215920 kb
Host smart-895a536f-9add-47f7-a6ab-7c8f41186f02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107731865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.107731865 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/18.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.3954732118
Short name T1173
Test name
Test status
Simulation time 188354345 ps
CPU time 2.41 seconds
Started Jul 25 04:42:48 PM PDT 24
Finished Jul 25 04:42:51 PM PDT 24
Peak memory 215876 kb
Host smart-c708d564-996f-4202-9802-234fcf09a12e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954732118 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.3954
732118 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.234497472
Short name T1193
Test name
Test status
Simulation time 19092995 ps
CPU time 1.36 seconds
Started Jul 25 04:42:48 PM PDT 24
Finished Jul 25 04:42:49 PM PDT 24
Peak memory 218844 kb
Host smart-a33c086c-980e-4deb-9d5e-0567a8a631da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234497472 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.kmac_csr_mem_rw_with_rand_reset.234497472 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_rw.2174426998
Short name T1077
Test name
Test status
Simulation time 26916933 ps
CPU time 0.98 seconds
Started Jul 25 04:42:45 PM PDT 24
Finished Jul 25 04:42:46 PM PDT 24
Peak memory 215784 kb
Host smart-4231d743-ea33-44a3-9707-3f84e6638cf2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174426998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.2174426998 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_intr_test.1203279819
Short name T1085
Test name
Test status
Simulation time 40726661 ps
CPU time 0.81 seconds
Started Jul 25 04:42:47 PM PDT 24
Finished Jul 25 04:42:49 PM PDT 24
Peak memory 215832 kb
Host smart-4fdb0ab7-7440-4824-85b6-c28a3beb0e02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203279819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.1203279819 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.585717604
Short name T1180
Test name
Test status
Simulation time 239646365 ps
CPU time 2.65 seconds
Started Jul 25 04:42:54 PM PDT 24
Finished Jul 25 04:42:56 PM PDT 24
Peak memory 215944 kb
Host smart-dd2a32f5-c9f8-4f23-8201-d7020b7b2837
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585717604 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_csr
_outstanding.585717604 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.4200870309
Short name T94
Test name
Test status
Simulation time 156932406 ps
CPU time 1.38 seconds
Started Jul 25 04:42:50 PM PDT 24
Finished Jul 25 04:42:52 PM PDT 24
Peak memory 216056 kb
Host smart-a906ff62-fefe-4ef5-a574-b3bd02093717
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200870309 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg
_errors.4200870309 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.2294589809
Short name T1149
Test name
Test status
Simulation time 61094656 ps
CPU time 1.67 seconds
Started Jul 25 04:42:53 PM PDT 24
Finished Jul 25 04:42:55 PM PDT 24
Peak memory 218860 kb
Host smart-7cde0ca2-2ebe-4f26-af8c-6019d54d8dfb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294589809 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kma
c_shadow_reg_errors_with_csr_rw.2294589809 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_errors.3121541752
Short name T1094
Test name
Test status
Simulation time 795476923 ps
CPU time 1.6 seconds
Started Jul 25 04:42:48 PM PDT 24
Finished Jul 25 04:42:50 PM PDT 24
Peak memory 216032 kb
Host smart-b77441d1-4471-45a5-8f42-cdf6c317f28a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121541752 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.3121541752 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.4058578285
Short name T194
Test name
Test status
Simulation time 363266451 ps
CPU time 4.14 seconds
Started Jul 25 04:42:48 PM PDT 24
Finished Jul 25 04:42:53 PM PDT 24
Peak memory 215892 kb
Host smart-b6923306-096d-4fee-b688-fcd3ea5b87b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058578285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.4058
578285 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.1400419792
Short name T1128
Test name
Test status
Simulation time 234573890 ps
CPU time 4.64 seconds
Started Jul 25 04:42:24 PM PDT 24
Finished Jul 25 04:42:29 PM PDT 24
Peak memory 215928 kb
Host smart-ff61fad9-9ac0-416e-9b57-d9c8a67b6d11
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400419792 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.1400419
792 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.1503765658
Short name T1090
Test name
Test status
Simulation time 615396004 ps
CPU time 8.02 seconds
Started Jul 25 04:42:53 PM PDT 24
Finished Jul 25 04:43:01 PM PDT 24
Peak memory 215948 kb
Host smart-a80f9d22-eff7-4f73-816e-8e552b01d32a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503765658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.1503765
658 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.443509905
Short name T1196
Test name
Test status
Simulation time 262826503 ps
CPU time 1.19 seconds
Started Jul 25 04:42:47 PM PDT 24
Finished Jul 25 04:42:48 PM PDT 24
Peak memory 215892 kb
Host smart-f0fe6be6-c161-4e93-bd74-843c7f8299cc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443509905 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.44350990
5 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.2767697813
Short name T1095
Test name
Test status
Simulation time 76288777 ps
CPU time 1.56 seconds
Started Jul 25 04:42:14 PM PDT 24
Finished Jul 25 04:42:15 PM PDT 24
Peak memory 216892 kb
Host smart-2d871dd4-c7b3-4e5c-aa35-5dc59268d35d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767697813 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.kmac_csr_mem_rw_with_rand_reset.2767697813 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_rw.4272074945
Short name T1080
Test name
Test status
Simulation time 136705322 ps
CPU time 1.08 seconds
Started Jul 25 04:42:10 PM PDT 24
Finished Jul 25 04:42:11 PM PDT 24
Peak memory 215884 kb
Host smart-61f680de-90be-440a-9680-4c788d2b41c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272074945 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.4272074945 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_intr_test.3937202517
Short name T1206
Test name
Test status
Simulation time 19693096 ps
CPU time 0.81 seconds
Started Jul 25 04:42:32 PM PDT 24
Finished Jul 25 04:42:33 PM PDT 24
Peak memory 215832 kb
Host smart-3d79a3a6-336e-4f28-a376-d6457488c684
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937202517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.3937202517 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.3673711074
Short name T157
Test name
Test status
Simulation time 26748625 ps
CPU time 1.1 seconds
Started Jul 25 04:42:13 PM PDT 24
Finished Jul 25 04:42:14 PM PDT 24
Peak memory 215908 kb
Host smart-53625611-919d-4474-bf6b-80d21413c2cd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673711074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partia
l_access.3673711074 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_walk.1047303947
Short name T1083
Test name
Test status
Simulation time 18549048 ps
CPU time 0.76 seconds
Started Jul 25 04:42:54 PM PDT 24
Finished Jul 25 04:42:55 PM PDT 24
Peak memory 215872 kb
Host smart-3785e5ad-e809-44f8-853b-f2d60e5dc74d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047303947 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.1047303947
+enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.2196427407
Short name T1087
Test name
Test status
Simulation time 24244680 ps
CPU time 1.46 seconds
Started Jul 25 04:42:42 PM PDT 24
Finished Jul 25 04:42:43 PM PDT 24
Peak memory 215944 kb
Host smart-c63c15eb-6e3b-4b45-a611-dfb935d06599
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196427407 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr
_outstanding.2196427407 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.2087914285
Short name T1096
Test name
Test status
Simulation time 45552985 ps
CPU time 1.2 seconds
Started Jul 25 04:42:13 PM PDT 24
Finished Jul 25 04:42:14 PM PDT 24
Peak memory 216092 kb
Host smart-178c3cd1-ac3f-43ee-ac7d-148dd188f835
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087914285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_
errors.2087914285 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.2480920101
Short name T1185
Test name
Test status
Simulation time 45874152 ps
CPU time 2.21 seconds
Started Jul 25 04:42:58 PM PDT 24
Finished Jul 25 04:43:00 PM PDT 24
Peak memory 218616 kb
Host smart-4d41a807-acff-4524-b9a4-77a2a665d35d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480920101 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac
_shadow_reg_errors_with_csr_rw.2480920101 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_errors.1749084848
Short name T1158
Test name
Test status
Simulation time 206447036 ps
CPU time 2.7 seconds
Started Jul 25 04:42:14 PM PDT 24
Finished Jul 25 04:42:17 PM PDT 24
Peak memory 215984 kb
Host smart-4ecc786c-f734-4cc4-b601-2118f8cb8ec7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749084848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.1749084848 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.3200167960
Short name T133
Test name
Test status
Simulation time 381606006 ps
CPU time 4.68 seconds
Started Jul 25 04:42:14 PM PDT 24
Finished Jul 25 04:42:19 PM PDT 24
Peak memory 215820 kb
Host smart-8776853d-242f-406f-a8ee-6d3dd6a613d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200167960 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.32001
67960 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.kmac_intr_test.718206553
Short name T1213
Test name
Test status
Simulation time 39423822 ps
CPU time 0.79 seconds
Started Jul 25 04:42:57 PM PDT 24
Finished Jul 25 04:42:58 PM PDT 24
Peak memory 215772 kb
Host smart-89a27f55-0d07-4324-baae-cae2210fbfa2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718206553 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.718206553 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/20.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.kmac_intr_test.2793916216
Short name T1114
Test name
Test status
Simulation time 14692688 ps
CPU time 0.77 seconds
Started Jul 25 04:42:59 PM PDT 24
Finished Jul 25 04:43:00 PM PDT 24
Peak memory 215784 kb
Host smart-00ec75ef-8bc7-4d9c-90e2-c612daa308d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793916216 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.2793916216 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.kmac_intr_test.814568797
Short name T1170
Test name
Test status
Simulation time 16278959 ps
CPU time 0.79 seconds
Started Jul 25 04:42:49 PM PDT 24
Finished Jul 25 04:42:55 PM PDT 24
Peak memory 215816 kb
Host smart-2afd48b6-6e79-470b-92ad-8dc55a93d7ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814568797 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.814568797 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/22.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.kmac_intr_test.3005034894
Short name T1181
Test name
Test status
Simulation time 66728439 ps
CPU time 0.78 seconds
Started Jul 25 04:42:44 PM PDT 24
Finished Jul 25 04:42:45 PM PDT 24
Peak memory 215752 kb
Host smart-99babd97-73ef-473f-9ec1-095a24711cee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005034894 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.3005034894 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.kmac_intr_test.19549059
Short name T178
Test name
Test status
Simulation time 18887156 ps
CPU time 0.76 seconds
Started Jul 25 04:43:00 PM PDT 24
Finished Jul 25 04:43:01 PM PDT 24
Peak memory 215772 kb
Host smart-0c08b9ff-09f2-4218-8961-f21c35abe915
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19549059 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.19549059 +enable_mas
king=1 +sw_key_masked=0
Directory /workspace/24.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.kmac_intr_test.498204142
Short name T1127
Test name
Test status
Simulation time 28715732 ps
CPU time 0.82 seconds
Started Jul 25 04:42:47 PM PDT 24
Finished Jul 25 04:42:48 PM PDT 24
Peak memory 215788 kb
Host smart-9661d271-d700-465c-8556-d4dd76dcd053
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498204142 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.498204142 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/25.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.kmac_intr_test.2055411800
Short name T1117
Test name
Test status
Simulation time 17198317 ps
CPU time 0.86 seconds
Started Jul 25 04:42:48 PM PDT 24
Finished Jul 25 04:42:50 PM PDT 24
Peak memory 215720 kb
Host smart-b2afc492-e091-40ef-b9a0-e57509591581
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055411800 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.2055411800 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.kmac_intr_test.1688952491
Short name T1214
Test name
Test status
Simulation time 16960385 ps
CPU time 0.84 seconds
Started Jul 25 04:42:56 PM PDT 24
Finished Jul 25 04:42:57 PM PDT 24
Peak memory 215804 kb
Host smart-0a3e724c-9f29-45bc-afd6-f3255e577d82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688952491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.1688952491 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.kmac_intr_test.1998150692
Short name T1133
Test name
Test status
Simulation time 28044574 ps
CPU time 0.84 seconds
Started Jul 25 04:42:53 PM PDT 24
Finished Jul 25 04:42:54 PM PDT 24
Peak memory 215792 kb
Host smart-b31dfc64-8ddb-4dd6-9446-e52ee196e81f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998150692 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.1998150692 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.kmac_intr_test.846822823
Short name T1176
Test name
Test status
Simulation time 57170179 ps
CPU time 0.77 seconds
Started Jul 25 04:42:54 PM PDT 24
Finished Jul 25 04:42:55 PM PDT 24
Peak memory 215788 kb
Host smart-aa6c4d8b-7059-44d7-84a6-59656508f555
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846822823 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.846822823 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/29.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.1829254792
Short name T1076
Test name
Test status
Simulation time 282355074 ps
CPU time 4.57 seconds
Started Jul 25 04:42:40 PM PDT 24
Finished Jul 25 04:42:45 PM PDT 24
Peak memory 215812 kb
Host smart-832dd5dc-c219-48dd-8893-4f560e222a0e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829254792 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.1829254
792 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.2509151664
Short name T1153
Test name
Test status
Simulation time 896638307 ps
CPU time 9.95 seconds
Started Jul 25 04:42:47 PM PDT 24
Finished Jul 25 04:42:57 PM PDT 24
Peak memory 215948 kb
Host smart-0e89b7b4-3a18-4134-a3d2-fbe0e62e04b0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509151664 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.2509151
664 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.507995903
Short name T1132
Test name
Test status
Simulation time 38311323 ps
CPU time 0.97 seconds
Started Jul 25 04:42:32 PM PDT 24
Finished Jul 25 04:42:33 PM PDT 24
Peak memory 215732 kb
Host smart-56aeb2b8-1b1d-471e-93cc-ffb2caadcd16
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507995903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.50799590
3 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.3341925723
Short name T1115
Test name
Test status
Simulation time 36641706 ps
CPU time 2.26 seconds
Started Jul 25 04:42:45 PM PDT 24
Finished Jul 25 04:42:48 PM PDT 24
Peak memory 222292 kb
Host smart-cec7ecf9-cec4-4c59-9b2d-5527590d7932
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341925723 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.kmac_csr_mem_rw_with_rand_reset.3341925723 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_rw.2589174780
Short name T162
Test name
Test status
Simulation time 33016079 ps
CPU time 1.18 seconds
Started Jul 25 04:42:21 PM PDT 24
Finished Jul 25 04:42:22 PM PDT 24
Peak memory 215896 kb
Host smart-c646e5c3-288c-4193-80e1-cf3bcfc7ef4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589174780 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.2589174780 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_intr_test.3897461057
Short name T168
Test name
Test status
Simulation time 16088009 ps
CPU time 0.79 seconds
Started Jul 25 04:42:50 PM PDT 24
Finished Jul 25 04:42:51 PM PDT 24
Peak memory 215800 kb
Host smart-64c062a3-94b7-4c8e-8569-a63d438247c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897461057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.3897461057 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.2794371309
Short name T156
Test name
Test status
Simulation time 97210322 ps
CPU time 1.2 seconds
Started Jul 25 04:42:14 PM PDT 24
Finished Jul 25 04:42:16 PM PDT 24
Peak memory 215848 kb
Host smart-9b90acd0-61a9-4623-981f-8b85add8a6b7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794371309 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partia
l_access.2794371309 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_walk.1853825321
Short name T1190
Test name
Test status
Simulation time 18951699 ps
CPU time 0.76 seconds
Started Jul 25 04:42:21 PM PDT 24
Finished Jul 25 04:42:22 PM PDT 24
Peak memory 215760 kb
Host smart-b1afaec0-bd5b-41bc-87f6-33db9ea20c09
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853825321 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.1853825321
+enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.3574865678
Short name T1088
Test name
Test status
Simulation time 41075370 ps
CPU time 2.11 seconds
Started Jul 25 04:42:42 PM PDT 24
Finished Jul 25 04:42:44 PM PDT 24
Peak memory 215812 kb
Host smart-21fa0227-fcbf-4688-9f68-8e420033811c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574865678 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr
_outstanding.3574865678 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.1370011575
Short name T1219
Test name
Test status
Simulation time 65072100 ps
CPU time 1.32 seconds
Started Jul 25 04:42:25 PM PDT 24
Finished Jul 25 04:42:26 PM PDT 24
Peak memory 216324 kb
Host smart-0f7a72be-49c9-40fc-8c4e-839b38cc99c8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370011575 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_
errors.1370011575 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.2951396110
Short name T1108
Test name
Test status
Simulation time 376673897 ps
CPU time 2.76 seconds
Started Jul 25 04:42:58 PM PDT 24
Finished Jul 25 04:43:01 PM PDT 24
Peak memory 219664 kb
Host smart-bb3b44ba-a990-4c3b-9fcd-b9df4b45749e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951396110 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac
_shadow_reg_errors_with_csr_rw.2951396110 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_errors.3757091813
Short name T1140
Test name
Test status
Simulation time 86406377 ps
CPU time 2.48 seconds
Started Jul 25 04:42:11 PM PDT 24
Finished Jul 25 04:42:13 PM PDT 24
Peak memory 215984 kb
Host smart-c85c3f5a-1998-46fa-9b1f-bbeb2807eb02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757091813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.3757091813 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.3214640142
Short name T191
Test name
Test status
Simulation time 249495148 ps
CPU time 3.01 seconds
Started Jul 25 04:42:29 PM PDT 24
Finished Jul 25 04:42:32 PM PDT 24
Peak memory 215792 kb
Host smart-acdd4df7-7086-42ff-853c-69976cd716cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214640142 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.32146
40142 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.kmac_intr_test.3502773196
Short name T1097
Test name
Test status
Simulation time 25925084 ps
CPU time 0.82 seconds
Started Jul 25 04:43:02 PM PDT 24
Finished Jul 25 04:43:13 PM PDT 24
Peak memory 215792 kb
Host smart-fc1db298-5d4c-448b-9e2d-e6c5e5826143
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502773196 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.3502773196 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.kmac_intr_test.3774742041
Short name T1139
Test name
Test status
Simulation time 19006799 ps
CPU time 0.78 seconds
Started Jul 25 04:43:00 PM PDT 24
Finished Jul 25 04:43:01 PM PDT 24
Peak memory 215816 kb
Host smart-2527e5b6-d953-4c6d-8248-0288af332d25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774742041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.3774742041 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.kmac_intr_test.460924729
Short name T1146
Test name
Test status
Simulation time 23809516 ps
CPU time 0.79 seconds
Started Jul 25 04:42:52 PM PDT 24
Finished Jul 25 04:42:53 PM PDT 24
Peak memory 215832 kb
Host smart-72898e77-c666-475c-839f-ee9da3e3424b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460924729 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.460924729 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/32.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.kmac_intr_test.378155581
Short name T1111
Test name
Test status
Simulation time 24813837 ps
CPU time 0.8 seconds
Started Jul 25 04:42:50 PM PDT 24
Finished Jul 25 04:42:51 PM PDT 24
Peak memory 215788 kb
Host smart-f7099cd4-4fd7-4dd0-87a2-f2490196de88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378155581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.378155581 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/33.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.kmac_intr_test.2138587228
Short name T1187
Test name
Test status
Simulation time 52074912 ps
CPU time 0.8 seconds
Started Jul 25 04:42:51 PM PDT 24
Finished Jul 25 04:42:52 PM PDT 24
Peak memory 215840 kb
Host smart-6ba26283-b3b5-46ff-bc2d-0955f3526387
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138587228 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.2138587228 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.kmac_intr_test.2106019715
Short name T1129
Test name
Test status
Simulation time 19854526 ps
CPU time 0.85 seconds
Started Jul 25 04:42:52 PM PDT 24
Finished Jul 25 04:42:53 PM PDT 24
Peak memory 215744 kb
Host smart-d7ddc1e4-71ab-415f-bc59-beb63b32b032
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106019715 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.2106019715 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.kmac_intr_test.4196921263
Short name T1189
Test name
Test status
Simulation time 18013695 ps
CPU time 0.79 seconds
Started Jul 25 04:42:57 PM PDT 24
Finished Jul 25 04:42:58 PM PDT 24
Peak memory 215744 kb
Host smart-82bb3dcd-07a5-4797-a729-7650f28ce644
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196921263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.4196921263 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.kmac_intr_test.4003081486
Short name T1157
Test name
Test status
Simulation time 92178175 ps
CPU time 0.81 seconds
Started Jul 25 04:42:46 PM PDT 24
Finished Jul 25 04:42:47 PM PDT 24
Peak memory 215772 kb
Host smart-1e3a719b-1ee6-44b8-94a7-11c3c6ec6e32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003081486 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.4003081486 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.kmac_intr_test.1947479398
Short name T179
Test name
Test status
Simulation time 15336547 ps
CPU time 0.79 seconds
Started Jul 25 04:42:51 PM PDT 24
Finished Jul 25 04:42:52 PM PDT 24
Peak memory 215824 kb
Host smart-82862ffb-c6bc-474e-86c1-2e579c10bc04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947479398 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.1947479398 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.kmac_intr_test.1232675976
Short name T1211
Test name
Test status
Simulation time 21631426 ps
CPU time 0.8 seconds
Started Jul 25 04:42:49 PM PDT 24
Finished Jul 25 04:42:50 PM PDT 24
Peak memory 215808 kb
Host smart-3958370e-0234-4dc7-bde7-136b9b2f6801
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232675976 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.1232675976 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.1645003872
Short name T1102
Test name
Test status
Simulation time 144081982 ps
CPU time 8.2 seconds
Started Jul 25 04:42:56 PM PDT 24
Finished Jul 25 04:43:04 PM PDT 24
Peak memory 215872 kb
Host smart-de1e14ff-aa27-4e9b-b7e1-ef473f590e8c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645003872 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.1645003
872 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.3367896362
Short name T166
Test name
Test status
Simulation time 3013853522 ps
CPU time 10.5 seconds
Started Jul 25 04:42:30 PM PDT 24
Finished Jul 25 04:42:41 PM PDT 24
Peak memory 216012 kb
Host smart-dad3c987-6efd-4791-b8f0-819f89c36856
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367896362 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.3367896
362 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.3287061250
Short name T1147
Test name
Test status
Simulation time 62054914 ps
CPU time 1.14 seconds
Started Jul 25 04:42:28 PM PDT 24
Finished Jul 25 04:42:30 PM PDT 24
Peak memory 216116 kb
Host smart-8c6dc573-bb3e-47d8-9405-fdf6b3da4242
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287061250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.3287061
250 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.1911874052
Short name T1205
Test name
Test status
Simulation time 81055254 ps
CPU time 2.23 seconds
Started Jul 25 04:42:45 PM PDT 24
Finished Jul 25 04:42:48 PM PDT 24
Peak memory 221524 kb
Host smart-fdc8d5e6-d7be-47a2-b578-4761407af882
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911874052 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.kmac_csr_mem_rw_with_rand_reset.1911874052 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_rw.3380409553
Short name T1134
Test name
Test status
Simulation time 73085373 ps
CPU time 0.95 seconds
Started Jul 25 04:42:42 PM PDT 24
Finished Jul 25 04:42:43 PM PDT 24
Peak memory 215804 kb
Host smart-1eeb3be1-4a45-47fc-8010-86294855d3d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380409553 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.3380409553 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_intr_test.1610472240
Short name T1199
Test name
Test status
Simulation time 40967552 ps
CPU time 0.8 seconds
Started Jul 25 04:42:59 PM PDT 24
Finished Jul 25 04:43:00 PM PDT 24
Peak memory 215788 kb
Host smart-611fa7c3-e093-4262-8a9c-ab1cb31bd23d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610472240 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.1610472240 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.3972130709
Short name T158
Test name
Test status
Simulation time 35702798 ps
CPU time 1.22 seconds
Started Jul 25 04:42:19 PM PDT 24
Finished Jul 25 04:42:21 PM PDT 24
Peak memory 215828 kb
Host smart-e010dcc1-9715-4385-9bf4-8883d8f18f18
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972130709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partia
l_access.3972130709 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_walk.405021961
Short name T1210
Test name
Test status
Simulation time 17439266 ps
CPU time 0.75 seconds
Started Jul 25 04:42:26 PM PDT 24
Finished Jul 25 04:42:28 PM PDT 24
Peak memory 215856 kb
Host smart-a4eda6ef-b405-4ccc-9bad-a7881622eaf8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405021961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.405021961 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.1682670835
Short name T1138
Test name
Test status
Simulation time 121761704 ps
CPU time 2.03 seconds
Started Jul 25 04:42:29 PM PDT 24
Finished Jul 25 04:42:31 PM PDT 24
Peak memory 215880 kb
Host smart-43ad173e-3daa-41f7-9544-40cb9d6f3df5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682670835 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr
_outstanding.1682670835 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.3924248298
Short name T1207
Test name
Test status
Simulation time 41779171 ps
CPU time 1.27 seconds
Started Jul 25 04:42:33 PM PDT 24
Finished Jul 25 04:42:39 PM PDT 24
Peak memory 217124 kb
Host smart-a2090294-bdcf-4896-bdb2-b921d81feb11
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924248298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_
errors.3924248298 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.4193342301
Short name T1182
Test name
Test status
Simulation time 89596546 ps
CPU time 2.54 seconds
Started Jul 25 04:42:25 PM PDT 24
Finished Jul 25 04:42:27 PM PDT 24
Peak memory 219596 kb
Host smart-39d60bee-1880-4b63-8935-517556b4e4af
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193342301 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac
_shadow_reg_errors_with_csr_rw.4193342301 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_errors.492835391
Short name T1200
Test name
Test status
Simulation time 132691169 ps
CPU time 3.36 seconds
Started Jul 25 04:42:48 PM PDT 24
Finished Jul 25 04:42:52 PM PDT 24
Peak memory 215940 kb
Host smart-6cd85535-21c6-46eb-9a9e-fe51533367e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492835391 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.492835391 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/4.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.1163218325
Short name T1161
Test name
Test status
Simulation time 227894798 ps
CPU time 4.69 seconds
Started Jul 25 04:42:58 PM PDT 24
Finished Jul 25 04:43:03 PM PDT 24
Peak memory 215840 kb
Host smart-4e55cc92-6b3b-4047-883d-f5a372dc9b96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163218325 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.11632
18325 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.kmac_intr_test.3962338760
Short name T167
Test name
Test status
Simulation time 38670871 ps
CPU time 0.83 seconds
Started Jul 25 04:42:46 PM PDT 24
Finished Jul 25 04:42:47 PM PDT 24
Peak memory 215820 kb
Host smart-981c8a1c-7e74-46e8-a9f9-9458371d49bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962338760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.3962338760 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.kmac_intr_test.1707458135
Short name T177
Test name
Test status
Simulation time 29358616 ps
CPU time 0.79 seconds
Started Jul 25 04:43:01 PM PDT 24
Finished Jul 25 04:43:02 PM PDT 24
Peak memory 215780 kb
Host smart-40177008-af57-4fad-b79c-88be18f081af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707458135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.1707458135 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.kmac_intr_test.602551989
Short name T1155
Test name
Test status
Simulation time 31390457 ps
CPU time 0.79 seconds
Started Jul 25 04:42:45 PM PDT 24
Finished Jul 25 04:42:45 PM PDT 24
Peak memory 215812 kb
Host smart-a5e7409e-24cb-40ed-b326-b1d03a5170d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602551989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.602551989 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/42.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.kmac_intr_test.2875897856
Short name T136
Test name
Test status
Simulation time 14112197 ps
CPU time 0.81 seconds
Started Jul 25 04:42:43 PM PDT 24
Finished Jul 25 04:42:44 PM PDT 24
Peak memory 215804 kb
Host smart-26926b97-03fb-41e0-a81f-0adf9df4aa1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875897856 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.2875897856 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.kmac_intr_test.2880619450
Short name T1084
Test name
Test status
Simulation time 14288519 ps
CPU time 0.78 seconds
Started Jul 25 04:43:01 PM PDT 24
Finished Jul 25 04:43:12 PM PDT 24
Peak memory 215812 kb
Host smart-4e518eaa-4d94-41e4-a183-49707dc2ba80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880619450 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.2880619450 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.kmac_intr_test.860955352
Short name T1105
Test name
Test status
Simulation time 15294476 ps
CPU time 0.77 seconds
Started Jul 25 04:43:01 PM PDT 24
Finished Jul 25 04:43:02 PM PDT 24
Peak memory 215788 kb
Host smart-9e6158d8-0501-4ed4-8675-96e972f60970
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860955352 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.860955352 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/45.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.kmac_intr_test.297402238
Short name T1215
Test name
Test status
Simulation time 22848945 ps
CPU time 0.81 seconds
Started Jul 25 04:43:01 PM PDT 24
Finished Jul 25 04:43:01 PM PDT 24
Peak memory 215828 kb
Host smart-c2954e77-8dd7-4724-8644-3f1c1de1e4fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297402238 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.297402238 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/46.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.kmac_intr_test.3867050105
Short name T1225
Test name
Test status
Simulation time 32700975 ps
CPU time 0.77 seconds
Started Jul 25 04:43:01 PM PDT 24
Finished Jul 25 04:43:02 PM PDT 24
Peak memory 215792 kb
Host smart-8683ed7d-f51e-456c-a294-b01177fdf46f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867050105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.3867050105 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.kmac_intr_test.869225619
Short name T1106
Test name
Test status
Simulation time 137392041 ps
CPU time 0.76 seconds
Started Jul 25 04:43:01 PM PDT 24
Finished Jul 25 04:43:02 PM PDT 24
Peak memory 215836 kb
Host smart-888d5ac2-3fa4-4fd6-a08b-78ceb836db3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869225619 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.869225619 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/48.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.kmac_intr_test.374394278
Short name T1143
Test name
Test status
Simulation time 11689564 ps
CPU time 0.78 seconds
Started Jul 25 04:43:03 PM PDT 24
Finished Jul 25 04:43:04 PM PDT 24
Peak memory 215840 kb
Host smart-3761ce66-3415-45f6-8524-1c84c46401c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374394278 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.374394278 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/49.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.212415475
Short name T1098
Test name
Test status
Simulation time 37852531 ps
CPU time 1.53 seconds
Started Jul 25 04:42:38 PM PDT 24
Finished Jul 25 04:42:40 PM PDT 24
Peak memory 216900 kb
Host smart-c4ce6b48-82a5-4a80-acba-f8341e19cecd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212415475 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.kmac_csr_mem_rw_with_rand_reset.212415475 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_rw.3302191181
Short name T1175
Test name
Test status
Simulation time 40679439 ps
CPU time 1.1 seconds
Started Jul 25 04:42:39 PM PDT 24
Finished Jul 25 04:42:40 PM PDT 24
Peak memory 215876 kb
Host smart-a34d4874-80bb-4102-a046-1362e0afc8e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302191181 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.3302191181 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_intr_test.2813509022
Short name T169
Test name
Test status
Simulation time 14079660 ps
CPU time 0.78 seconds
Started Jul 25 04:42:25 PM PDT 24
Finished Jul 25 04:42:26 PM PDT 24
Peak memory 215988 kb
Host smart-b2d6a28d-c9ac-4f68-b35d-4cf67990599c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813509022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.2813509022 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.3725091382
Short name T1119
Test name
Test status
Simulation time 49654470 ps
CPU time 1.55 seconds
Started Jul 25 04:42:20 PM PDT 24
Finished Jul 25 04:42:22 PM PDT 24
Peak memory 215828 kb
Host smart-6b519867-a0eb-43d9-842a-6b1beb5cd96f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725091382 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr
_outstanding.3725091382 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.406042312
Short name T1202
Test name
Test status
Simulation time 19056523 ps
CPU time 1.12 seconds
Started Jul 25 04:42:44 PM PDT 24
Finished Jul 25 04:42:45 PM PDT 24
Peak memory 217236 kb
Host smart-bf8634c5-209c-450e-b686-6685ba86d9ec
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406042312 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_e
rrors.406042312 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.1344165879
Short name T1171
Test name
Test status
Simulation time 93489581 ps
CPU time 1.57 seconds
Started Jul 25 04:42:38 PM PDT 24
Finished Jul 25 04:42:40 PM PDT 24
Peak memory 215892 kb
Host smart-d39d8485-4343-4493-9786-428c5ed81a0b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344165879 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac
_shadow_reg_errors_with_csr_rw.1344165879 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_errors.4041643568
Short name T1120
Test name
Test status
Simulation time 314977268 ps
CPU time 3.89 seconds
Started Jul 25 04:42:15 PM PDT 24
Finished Jul 25 04:42:19 PM PDT 24
Peak memory 215932 kb
Host smart-d2ecdb59-66c0-4294-9d4e-b6f8f3aeaeef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041643568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.4041643568 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.40710994
Short name T186
Test name
Test status
Simulation time 337197069 ps
CPU time 2.49 seconds
Started Jul 25 04:42:45 PM PDT 24
Finished Jul 25 04:42:48 PM PDT 24
Peak memory 215828 kb
Host smart-98d3cdd8-63c3-40de-9a6f-0db014f312f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40710994 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.4071099
4 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.248846135
Short name T163
Test name
Test status
Simulation time 161817359 ps
CPU time 1.57 seconds
Started Jul 25 04:42:46 PM PDT 24
Finished Jul 25 04:42:48 PM PDT 24
Peak memory 217460 kb
Host smart-0beea382-2031-4132-b5ed-0f496b51c0a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248846135 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.kmac_csr_mem_rw_with_rand_reset.248846135 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_rw.1495487148
Short name T1226
Test name
Test status
Simulation time 29981103 ps
CPU time 1.14 seconds
Started Jul 25 04:42:25 PM PDT 24
Finished Jul 25 04:42:26 PM PDT 24
Peak memory 215872 kb
Host smart-32ed156f-4d0b-426f-bdc9-03ddb66d6954
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495487148 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.1495487148 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_intr_test.3499307235
Short name T1136
Test name
Test status
Simulation time 11468592 ps
CPU time 0.73 seconds
Started Jul 25 04:42:18 PM PDT 24
Finished Jul 25 04:42:18 PM PDT 24
Peak memory 215796 kb
Host smart-f96c9242-4dd2-492e-bb84-d1c781ba23b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499307235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.3499307235 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.901672353
Short name T161
Test name
Test status
Simulation time 102555749 ps
CPU time 2.32 seconds
Started Jul 25 04:42:16 PM PDT 24
Finished Jul 25 04:42:19 PM PDT 24
Peak memory 215836 kb
Host smart-b58c6d4e-eccb-4304-bd13-7cf46b5216ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901672353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr_
outstanding.901672353 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.2600074088
Short name T1218
Test name
Test status
Simulation time 52363690 ps
CPU time 2.59 seconds
Started Jul 25 04:42:29 PM PDT 24
Finished Jul 25 04:42:32 PM PDT 24
Peak memory 219188 kb
Host smart-24a3d770-bf67-4648-991d-0db1a3cb0c1c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600074088 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac
_shadow_reg_errors_with_csr_rw.2600074088 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_errors.1748637648
Short name T1198
Test name
Test status
Simulation time 71319493 ps
CPU time 1.84 seconds
Started Jul 25 04:42:16 PM PDT 24
Finished Jul 25 04:42:18 PM PDT 24
Peak memory 215936 kb
Host smart-0c0849e0-1935-4d3d-b6e6-db9488abae9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748637648 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.1748637648 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.876009028
Short name T1081
Test name
Test status
Simulation time 277666365 ps
CPU time 2.47 seconds
Started Jul 25 04:42:20 PM PDT 24
Finished Jul 25 04:42:23 PM PDT 24
Peak memory 221392 kb
Host smart-f7a090d1-f805-4888-978b-41de62b78eda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876009028 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.kmac_csr_mem_rw_with_rand_reset.876009028 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_rw.3592851095
Short name T1188
Test name
Test status
Simulation time 17516859 ps
CPU time 1.1 seconds
Started Jul 25 04:42:36 PM PDT 24
Finished Jul 25 04:42:37 PM PDT 24
Peak memory 215924 kb
Host smart-20e4e9c9-38dd-44f5-a350-16aeffbd492a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592851095 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.3592851095 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_intr_test.700093852
Short name T1109
Test name
Test status
Simulation time 13411298 ps
CPU time 0.76 seconds
Started Jul 25 04:42:45 PM PDT 24
Finished Jul 25 04:42:46 PM PDT 24
Peak memory 215848 kb
Host smart-fb113578-f8a9-4138-9a8a-c2801a3cbccf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700093852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.700093852 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/7.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.2809361128
Short name T1212
Test name
Test status
Simulation time 373185513 ps
CPU time 2.6 seconds
Started Jul 25 04:42:46 PM PDT 24
Finished Jul 25 04:42:54 PM PDT 24
Peak memory 215888 kb
Host smart-87f9a4b0-1ab8-4369-af7b-2a6cf43492d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809361128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr
_outstanding.2809361128 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.1782507937
Short name T171
Test name
Test status
Simulation time 111893701 ps
CPU time 1.54 seconds
Started Jul 25 04:42:13 PM PDT 24
Finished Jul 25 04:42:15 PM PDT 24
Peak memory 216380 kb
Host smart-c34c2174-2ba9-4144-b9b4-3791709992a4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782507937 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_
errors.1782507937 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.930844909
Short name T1167
Test name
Test status
Simulation time 29590939 ps
CPU time 1.62 seconds
Started Jul 25 04:42:48 PM PDT 24
Finished Jul 25 04:42:50 PM PDT 24
Peak memory 215844 kb
Host smart-a6867884-3e6e-4b1d-b058-b9a9b8896223
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930844909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_
shadow_reg_errors_with_csr_rw.930844909 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_errors.819691479
Short name T1122
Test name
Test status
Simulation time 604871603 ps
CPU time 2.77 seconds
Started Jul 25 04:42:55 PM PDT 24
Finished Jul 25 04:42:58 PM PDT 24
Peak memory 215996 kb
Host smart-93adcccb-81d0-475c-b02c-62a8d033e08a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819691479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.819691479 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/7.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.2205837868
Short name T1183
Test name
Test status
Simulation time 265599794 ps
CPU time 4.43 seconds
Started Jul 25 04:42:29 PM PDT 24
Finished Jul 25 04:42:34 PM PDT 24
Peak memory 215156 kb
Host smart-67f5cd3c-3a73-4ddd-8937-96b78d5f82f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205837868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.22058
37868 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.4129582622
Short name T1124
Test name
Test status
Simulation time 23840448 ps
CPU time 1.7 seconds
Started Jul 25 04:42:22 PM PDT 24
Finished Jul 25 04:42:24 PM PDT 24
Peak memory 220400 kb
Host smart-afb3399e-f1e3-4751-80fc-733acf4a05e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129582622 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.kmac_csr_mem_rw_with_rand_reset.4129582622 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_rw.525116719
Short name T1168
Test name
Test status
Simulation time 36712190 ps
CPU time 0.93 seconds
Started Jul 25 04:42:29 PM PDT 24
Finished Jul 25 04:42:30 PM PDT 24
Peak memory 215736 kb
Host smart-2824a5eb-99ce-4b26-8bdd-0d3aca6bb1bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525116719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.525116719 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/8.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_intr_test.3055572929
Short name T1217
Test name
Test status
Simulation time 28324071 ps
CPU time 0.83 seconds
Started Jul 25 04:42:11 PM PDT 24
Finished Jul 25 04:42:12 PM PDT 24
Peak memory 215736 kb
Host smart-d0d69c70-df3f-4cc8-b410-7f973e50e499
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055572929 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.3055572929 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.1539806631
Short name T1079
Test name
Test status
Simulation time 138548439 ps
CPU time 2.52 seconds
Started Jul 25 04:42:53 PM PDT 24
Finished Jul 25 04:42:56 PM PDT 24
Peak memory 215924 kb
Host smart-1cdc4dbc-1c5b-4084-a70d-65039ab1b982
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539806631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr
_outstanding.1539806631 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.393191266
Short name T1165
Test name
Test status
Simulation time 28690624 ps
CPU time 1.14 seconds
Started Jul 25 04:42:55 PM PDT 24
Finished Jul 25 04:42:56 PM PDT 24
Peak memory 216416 kb
Host smart-cae15134-365b-4614-9c87-95bc5d292a22
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393191266 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_e
rrors.393191266 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.2018319790
Short name T1116
Test name
Test status
Simulation time 50188336 ps
CPU time 1.67 seconds
Started Jul 25 04:43:00 PM PDT 24
Finished Jul 25 04:43:02 PM PDT 24
Peak memory 216112 kb
Host smart-66409a3c-3a77-411d-9033-f6542c3c7a9f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018319790 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac
_shadow_reg_errors_with_csr_rw.2018319790 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_errors.4188088713
Short name T1152
Test name
Test status
Simulation time 144163418 ps
CPU time 3 seconds
Started Jul 25 04:42:33 PM PDT 24
Finished Jul 25 04:42:36 PM PDT 24
Peak memory 215952 kb
Host smart-d59bc8c3-2aa9-45ec-8cc0-4aec6c9550a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188088713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.4188088713 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.3855026113
Short name T1227
Test name
Test status
Simulation time 188117403 ps
CPU time 4.48 seconds
Started Jul 25 04:42:14 PM PDT 24
Finished Jul 25 04:42:19 PM PDT 24
Peak memory 215888 kb
Host smart-69542527-6bfb-4268-b711-e5b6138282e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855026113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.38550
26113 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.662772957
Short name T1121
Test name
Test status
Simulation time 165901542 ps
CPU time 1.62 seconds
Started Jul 25 04:42:48 PM PDT 24
Finished Jul 25 04:42:50 PM PDT 24
Peak memory 216416 kb
Host smart-1d9205f0-e8f0-40c7-a21d-09f3a0bb695f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662772957 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.kmac_csr_mem_rw_with_rand_reset.662772957 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_rw.1853387176
Short name T1135
Test name
Test status
Simulation time 184964402 ps
CPU time 0.96 seconds
Started Jul 25 04:42:53 PM PDT 24
Finished Jul 25 04:42:54 PM PDT 24
Peak memory 215780 kb
Host smart-259e3c6b-7b94-4d0e-93ac-65e587299a75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853387176 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.1853387176 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_intr_test.2095697109
Short name T135
Test name
Test status
Simulation time 14170268 ps
CPU time 0.76 seconds
Started Jul 25 04:42:21 PM PDT 24
Finished Jul 25 04:42:21 PM PDT 24
Peak memory 215868 kb
Host smart-d026e533-b3c3-46f4-b87c-61447462abcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095697109 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.2095697109 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.2334729470
Short name T1099
Test name
Test status
Simulation time 26373482 ps
CPU time 1.49 seconds
Started Jul 25 04:42:50 PM PDT 24
Finished Jul 25 04:42:51 PM PDT 24
Peak memory 215828 kb
Host smart-979ec740-b439-493c-92d6-a72b44fe9f97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334729470 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr
_outstanding.2334729470 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.2947154287
Short name T197
Test name
Test status
Simulation time 29766023 ps
CPU time 1.16 seconds
Started Jul 25 04:42:51 PM PDT 24
Finished Jul 25 04:42:52 PM PDT 24
Peak memory 216200 kb
Host smart-058ec3af-78b6-4a33-971d-f1f50ce08d44
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947154287 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_
errors.2947154287 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.816983126
Short name T88
Test name
Test status
Simulation time 240515748 ps
CPU time 2.83 seconds
Started Jul 25 04:42:15 PM PDT 24
Finished Jul 25 04:42:18 PM PDT 24
Peak memory 219328 kb
Host smart-0b12832a-85f0-42fa-be4d-4e9f2ba8d64e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816983126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_
shadow_reg_errors_with_csr_rw.816983126 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_errors.3918517297
Short name T1086
Test name
Test status
Simulation time 59546469 ps
CPU time 2.89 seconds
Started Jul 25 04:42:29 PM PDT 24
Finished Jul 25 04:42:32 PM PDT 24
Peak memory 215924 kb
Host smart-3e43a0b1-66f6-4dcd-9b17-d8a66e100ecd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918517297 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.3918517297 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.3132641204
Short name T193
Test name
Test status
Simulation time 104839508 ps
CPU time 2.42 seconds
Started Jul 25 04:42:46 PM PDT 24
Finished Jul 25 04:42:48 PM PDT 24
Peak memory 215860 kb
Host smart-6124f682-50d9-43e7-8b97-62d969603752
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132641204 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.31326
41204 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.kmac_alert_test.105497385
Short name T692
Test name
Test status
Simulation time 66050269 ps
CPU time 0.89 seconds
Started Jul 25 05:11:54 PM PDT 24
Finished Jul 25 05:11:55 PM PDT 24
Peak memory 218276 kb
Host smart-af190798-797d-4b34-a9b0-db72ede30347
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105497385 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.105497385 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/0.kmac_alert_test/latest

Test location /workspace/coverage/default/0.kmac_app.3244618220
Short name T640
Test name
Test status
Simulation time 6124800033 ps
CPU time 86.73 seconds
Started Jul 25 05:11:49 PM PDT 24
Finished Jul 25 05:13:16 PM PDT 24
Peak memory 231108 kb
Host smart-6e7b9009-2d3e-4a28-b1fd-d7bd74dc9175
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244618220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.3244618220 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/0.kmac_app/latest

Test location /workspace/coverage/default/0.kmac_app_with_partial_data.59699970
Short name T427
Test name
Test status
Simulation time 1866892172 ps
CPU time 25.62 seconds
Started Jul 25 05:11:48 PM PDT 24
Finished Jul 25 05:12:14 PM PDT 24
Peak memory 226700 kb
Host smart-16928db8-6749-4507-b69b-201ab3338fe9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59699970 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partia
l_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_parti
al_data.59699970 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/0.kmac_burst_write.1319391362
Short name T996
Test name
Test status
Simulation time 888368567 ps
CPU time 40.2 seconds
Started Jul 25 05:11:47 PM PDT 24
Finished Jul 25 05:12:28 PM PDT 24
Peak memory 226528 kb
Host smart-7d40ce08-d3b8-4926-8679-c7c23113456e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319391362 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.1319391362
+enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_burst_write/latest

Test location /workspace/coverage/default/0.kmac_edn_timeout_error.3557987886
Short name T565
Test name
Test status
Simulation time 3077234840 ps
CPU time 39.36 seconds
Started Jul 25 05:11:48 PM PDT 24
Finished Jul 25 05:12:27 PM PDT 24
Peak memory 242856 kb
Host smart-2d8cb77a-ed45-41cd-8d5a-2864be01658a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3557987886 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.3557987886 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_ready_error.345669437
Short name T644
Test name
Test status
Simulation time 1407244189 ps
CPU time 7.14 seconds
Started Jul 25 05:11:48 PM PDT 24
Finished Jul 25 05:11:55 PM PDT 24
Peak memory 218564 kb
Host smart-c69a6880-a251-46a9-879e-01c77483e44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345669437 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.345669437 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_refresh.165188887
Short name T839
Test name
Test status
Simulation time 6168092135 ps
CPU time 353.79 seconds
Started Jul 25 05:11:53 PM PDT 24
Finished Jul 25 05:17:47 PM PDT 24
Peak memory 252748 kb
Host smart-ff1b57d2-ca7b-4a02-ba22-16311f0d4d25
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165188887 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.165
188887 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/0.kmac_error.2058628522
Short name T26
Test name
Test status
Simulation time 20517534654 ps
CPU time 530.82 seconds
Started Jul 25 05:11:45 PM PDT 24
Finished Jul 25 05:20:36 PM PDT 24
Peak memory 259440 kb
Host smart-818d1285-60fd-469a-8b33-0223b3eb47e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058628522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.2058628522 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_error/latest

Test location /workspace/coverage/default/0.kmac_key_error.153349034
Short name T6
Test name
Test status
Simulation time 263602733 ps
CPU time 1.83 seconds
Started Jul 25 05:11:57 PM PDT 24
Finished Jul 25 05:11:59 PM PDT 24
Peak memory 218388 kb
Host smart-c29e1265-d84e-474e-8fb7-99dbc91e4025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153349034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.153349034 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_key_error/latest

Test location /workspace/coverage/default/0.kmac_long_msg_and_output.3668114798
Short name T555
Test name
Test status
Simulation time 73959689442 ps
CPU time 614.77 seconds
Started Jul 25 05:11:48 PM PDT 24
Finished Jul 25 05:22:03 PM PDT 24
Peak memory 273096 kb
Host smart-5d934041-a348-4c28-a2cf-b73f40a23ab4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668114798 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_an
d_output.3668114798 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/0.kmac_mubi.3965018709
Short name T720
Test name
Test status
Simulation time 22466038617 ps
CPU time 413.79 seconds
Started Jul 25 05:11:58 PM PDT 24
Finished Jul 25 05:18:52 PM PDT 24
Peak memory 254956 kb
Host smart-65789218-6862-4b9b-8689-35fbfb1e73a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965018709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.3965018709 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_mubi/latest

Test location /workspace/coverage/default/0.kmac_sideload.1913779593
Short name T742
Test name
Test status
Simulation time 75845468 ps
CPU time 4.75 seconds
Started Jul 25 05:11:57 PM PDT 24
Finished Jul 25 05:12:02 PM PDT 24
Peak memory 221368 kb
Host smart-4e6e5082-1cf5-4151-a664-c0ccfec04d44
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913779593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.1913779593 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_sideload/latest

Test location /workspace/coverage/default/0.kmac_smoke.3903397811
Short name T144
Test name
Test status
Simulation time 6538298872 ps
CPU time 56.45 seconds
Started Jul 25 05:11:48 PM PDT 24
Finished Jul 25 05:12:45 PM PDT 24
Peak memory 222948 kb
Host smart-2441f291-643d-4628-90f5-742647f755f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903397811 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.3903397811 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_smoke/latest

Test location /workspace/coverage/default/0.kmac_stress_all.490039348
Short name T597
Test name
Test status
Simulation time 38505016971 ps
CPU time 772.71 seconds
Started Jul 25 05:11:58 PM PDT 24
Finished Jul 25 05:24:51 PM PDT 24
Peak memory 325892 kb
Host smart-5ef0950f-9402-44cf-8d25-a75e1ed2857c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=490039348 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.490039348 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_stress_all/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac.224147720
Short name T210
Test name
Test status
Simulation time 264808399 ps
CPU time 5.82 seconds
Started Jul 25 05:11:50 PM PDT 24
Finished Jul 25 05:11:56 PM PDT 24
Peak memory 218452 kb
Host smart-785b9318-17b3-41ae-9756-a47bd6d153f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224147720 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.kmac_test_vectors_kmac.224147720 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac_xof.2322025438
Short name T258
Test name
Test status
Simulation time 113136866 ps
CPU time 5.86 seconds
Started Jul 25 05:11:46 PM PDT 24
Finished Jul 25 05:11:52 PM PDT 24
Peak memory 218436 kb
Host smart-e39019a7-2393-4f64-9dba-3da400d6a7b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322025438 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.kmac_test_vectors_kmac_xof.2322025438 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_224.1998798004
Short name T868
Test name
Test status
Simulation time 400884541486 ps
CPU time 2328.19 seconds
Started Jul 25 05:11:47 PM PDT 24
Finished Jul 25 05:50:36 PM PDT 24
Peak memory 393028 kb
Host smart-77c50a51-cbfd-4e71-aff1-e2335b49ecd5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1998798004 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.1998798004 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_256.661207851
Short name T303
Test name
Test status
Simulation time 97984460058 ps
CPU time 2096.59 seconds
Started Jul 25 05:11:58 PM PDT 24
Finished Jul 25 05:46:55 PM PDT 24
Peak memory 391856 kb
Host smart-dee4c524-56eb-49c7-8226-0bb232ef6dcf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=661207851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.661207851 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_384.716567277
Short name T611
Test name
Test status
Simulation time 47260981670 ps
CPU time 1558.08 seconds
Started Jul 25 05:11:47 PM PDT 24
Finished Jul 25 05:37:46 PM PDT 24
Peak memory 338000 kb
Host smart-fcfeaa5a-0a31-4f97-95ec-8f5f8ff3e853
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=716567277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.716567277 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_512.3640995497
Short name T419
Test name
Test status
Simulation time 69625953269 ps
CPU time 1290.24 seconds
Started Jul 25 05:11:47 PM PDT 24
Finished Jul 25 05:33:17 PM PDT 24
Peak memory 301372 kb
Host smart-c3e931e5-fd56-43c2-901d-9f63c3cdcb97
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3640995497 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.3640995497 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_128.4133129681
Short name T215
Test name
Test status
Simulation time 807245742886 ps
CPU time 5298.78 seconds
Started Jul 25 05:11:49 PM PDT 24
Finished Jul 25 06:40:08 PM PDT 24
Peak memory 644040 kb
Host smart-954384b2-99f1-4f8e-8c3d-007560978de7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4133129681 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.4133129681 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_256.655695808
Short name T545
Test name
Test status
Simulation time 112061931215 ps
CPU time 4649.56 seconds
Started Jul 25 05:11:47 PM PDT 24
Finished Jul 25 06:29:18 PM PDT 24
Peak memory 578860 kb
Host smart-8d3549f3-aadc-4a57-8655-720f7f7ef007
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=655695808 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.655695808 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/1.kmac_alert_test.2621611188
Short name T632
Test name
Test status
Simulation time 54725277 ps
CPU time 0.77 seconds
Started Jul 25 05:11:57 PM PDT 24
Finished Jul 25 05:11:58 PM PDT 24
Peak memory 218252 kb
Host smart-b6969c29-2bc4-492d-9b7b-6a6d9435e365
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621611188 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.2621611188 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_alert_test/latest

Test location /workspace/coverage/default/1.kmac_app_with_partial_data.3388148202
Short name T786
Test name
Test status
Simulation time 5865195318 ps
CPU time 29.37 seconds
Started Jul 25 05:11:58 PM PDT 24
Finished Jul 25 05:12:28 PM PDT 24
Peak memory 226652 kb
Host smart-f9b48fcc-2322-460f-83c2-c87debb496fb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388148202 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_par
tial_data.3388148202 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/1.kmac_burst_write.1997255869
Short name T636
Test name
Test status
Simulation time 168666061401 ps
CPU time 1057.36 seconds
Started Jul 25 05:11:56 PM PDT 24
Finished Jul 25 05:29:34 PM PDT 24
Peak memory 243080 kb
Host smart-9811890b-d5c8-4dd7-9cb9-6ced2117c8c7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997255869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.1997255869
+enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_burst_write/latest

Test location /workspace/coverage/default/1.kmac_entropy_mode_error.1253814250
Short name T887
Test name
Test status
Simulation time 62165652 ps
CPU time 1.09 seconds
Started Jul 25 05:11:57 PM PDT 24
Finished Jul 25 05:11:58 PM PDT 24
Peak memory 221860 kb
Host smart-d677c7c1-22cd-4d45-a419-eb0aa60f3f55
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1253814250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.1253814250 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_refresh.3271944446
Short name T344
Test name
Test status
Simulation time 1683414704 ps
CPU time 14.44 seconds
Started Jul 25 05:12:00 PM PDT 24
Finished Jul 25 05:12:14 PM PDT 24
Peak memory 224968 kb
Host smart-c73047df-61b9-43b9-b0a8-5c013dbad298
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271944446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.32
71944446 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/1.kmac_error.269057350
Short name T27
Test name
Test status
Simulation time 6507258884 ps
CPU time 106.43 seconds
Started Jul 25 05:11:56 PM PDT 24
Finished Jul 25 05:13:42 PM PDT 24
Peak memory 243024 kb
Host smart-039e5e2d-5471-4299-a6f1-7562f449bdcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269057350 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.269057350 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_error/latest

Test location /workspace/coverage/default/1.kmac_key_error.624405161
Short name T920
Test name
Test status
Simulation time 536399142 ps
CPU time 4.18 seconds
Started Jul 25 05:11:57 PM PDT 24
Finished Jul 25 05:12:02 PM PDT 24
Peak memory 223100 kb
Host smart-fb7e5dd7-c284-4fc9-8371-a0b3f3b28e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624405161 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.624405161 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_key_error/latest

Test location /workspace/coverage/default/1.kmac_lc_escalation.1921881014
Short name T102
Test name
Test status
Simulation time 2184647840 ps
CPU time 11.7 seconds
Started Jul 25 05:11:56 PM PDT 24
Finished Jul 25 05:12:08 PM PDT 24
Peak memory 234968 kb
Host smart-141f96a4-7e4c-480f-9fa1-ab69e8af0a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921881014 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.1921881014 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/1.kmac_lc_escalation/latest

Test location /workspace/coverage/default/1.kmac_long_msg_and_output.105502428
Short name T628
Test name
Test status
Simulation time 27767845981 ps
CPU time 1493.11 seconds
Started Jul 25 05:11:57 PM PDT 24
Finished Jul 25 05:36:51 PM PDT 24
Peak memory 349144 kb
Host smart-39e9d45d-9fcb-4373-8545-44eb201f2cf7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105502428 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_and
_output.105502428 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/1.kmac_mubi.3863042038
Short name T785
Test name
Test status
Simulation time 3112128439 ps
CPU time 71.34 seconds
Started Jul 25 05:11:56 PM PDT 24
Finished Jul 25 05:13:07 PM PDT 24
Peak memory 230560 kb
Host smart-bb46ecaa-9155-4ed1-9c9e-02863d1bbd57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863042038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.3863042038 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_mubi/latest

Test location /workspace/coverage/default/1.kmac_sec_cm.186130
Short name T121
Test name
Test status
Simulation time 4328480448 ps
CPU time 68.79 seconds
Started Jul 25 05:12:00 PM PDT 24
Finished Jul 25 05:13:09 PM PDT 24
Peak memory 269544 kb
Host smart-8ae35518-af5b-4e15-918d-5432855c2374
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.186130 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/1.kmac_sec_cm/latest

Test location /workspace/coverage/default/1.kmac_sideload.2391587340
Short name T591
Test name
Test status
Simulation time 6347723771 ps
CPU time 26 seconds
Started Jul 25 05:11:57 PM PDT 24
Finished Jul 25 05:12:24 PM PDT 24
Peak memory 232632 kb
Host smart-76f14147-95eb-4c08-88c1-a995bf53b2e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391587340 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.2391587340 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_sideload/latest

Test location /workspace/coverage/default/1.kmac_smoke.3021232562
Short name T802
Test name
Test status
Simulation time 7085007890 ps
CPU time 42.46 seconds
Started Jul 25 05:11:59 PM PDT 24
Finished Jul 25 05:12:42 PM PDT 24
Peak memory 223432 kb
Host smart-c0e6192d-3fb6-414c-81ec-7d3b52660a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021232562 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.3021232562 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_smoke/latest

Test location /workspace/coverage/default/1.kmac_stress_all.2009417830
Short name T1029
Test name
Test status
Simulation time 452417834586 ps
CPU time 2813.23 seconds
Started Jul 25 05:11:59 PM PDT 24
Finished Jul 25 05:58:53 PM PDT 24
Peak memory 514260 kb
Host smart-80dbf0b1-9291-4617-a507-f6c7f604feac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2009417830 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.2009417830 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_stress_all/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac.1236033397
Short name T782
Test name
Test status
Simulation time 193595255 ps
CPU time 6.52 seconds
Started Jul 25 05:11:56 PM PDT 24
Finished Jul 25 05:12:03 PM PDT 24
Peak memory 218460 kb
Host smart-509a1075-fe12-4a28-bf08-085c46fe0a88
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236033397 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.kmac_test_vectors_kmac.1236033397 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac_xof.1281569517
Short name T796
Test name
Test status
Simulation time 255873879 ps
CPU time 6.51 seconds
Started Jul 25 05:11:58 PM PDT 24
Finished Jul 25 05:12:05 PM PDT 24
Peak memory 218584 kb
Host smart-0a0a8815-e7fb-4579-954e-3c3492c45e81
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281569517 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.kmac_test_vectors_kmac_xof.1281569517 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_224.626227983
Short name T445
Test name
Test status
Simulation time 84879249640 ps
CPU time 1894.84 seconds
Started Jul 25 05:11:55 PM PDT 24
Finished Jul 25 05:43:30 PM PDT 24
Peak memory 395448 kb
Host smart-ceee2465-7399-43ff-8ecf-ac39673d4a54
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=626227983 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.626227983 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_256.1777085031
Short name T249
Test name
Test status
Simulation time 62646136735 ps
CPU time 2069.23 seconds
Started Jul 25 05:11:56 PM PDT 24
Finished Jul 25 05:46:26 PM PDT 24
Peak memory 385624 kb
Host smart-ec64091b-d6e3-43f3-89cb-022c1e67a2c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1777085031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.1777085031 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_384.594746193
Short name T106
Test name
Test status
Simulation time 15383529575 ps
CPU time 1585.61 seconds
Started Jul 25 05:11:54 PM PDT 24
Finished Jul 25 05:38:20 PM PDT 24
Peak memory 338628 kb
Host smart-64ae4abc-9644-4668-9edc-1dd133d6693b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=594746193 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.594746193 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_512.1214266824
Short name T736
Test name
Test status
Simulation time 49451819855 ps
CPU time 1385.87 seconds
Started Jul 25 05:11:58 PM PDT 24
Finished Jul 25 05:35:04 PM PDT 24
Peak memory 301600 kb
Host smart-95e57cd1-dd5d-4a40-b58d-d8d28ac3addf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1214266824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.1214266824 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_shake_128.1139645580
Short name T357
Test name
Test status
Simulation time 61882976173 ps
CPU time 4809.22 seconds
Started Jul 25 05:11:56 PM PDT 24
Finished Jul 25 06:32:06 PM PDT 24
Peak memory 657620 kb
Host smart-527f1915-c055-4d7a-8796-5c149a19b4b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1139645580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.1139645580 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_shake_256.768174626
Short name T944
Test name
Test status
Simulation time 602919719052 ps
CPU time 4752.99 seconds
Started Jul 25 05:11:57 PM PDT 24
Finished Jul 25 06:31:11 PM PDT 24
Peak memory 571544 kb
Host smart-f929fd8e-3e4a-4f2c-9d63-3e6245180e77
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=768174626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.768174626 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/10.kmac_alert_test.3298545816
Short name T622
Test name
Test status
Simulation time 39165289 ps
CPU time 0.85 seconds
Started Jul 25 05:13:02 PM PDT 24
Finished Jul 25 05:13:02 PM PDT 24
Peak memory 218216 kb
Host smart-03a370c5-340d-4a83-873c-125ee8eb64ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298545816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.3298545816 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_alert_test/latest

Test location /workspace/coverage/default/10.kmac_app.213213847
Short name T947
Test name
Test status
Simulation time 96487549308 ps
CPU time 327.46 seconds
Started Jul 25 05:12:52 PM PDT 24
Finished Jul 25 05:18:19 PM PDT 24
Peak memory 250496 kb
Host smart-d0e46573-4b1b-419e-aca7-4508129f495b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213213847 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.213213847 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/10.kmac_app/latest

Test location /workspace/coverage/default/10.kmac_burst_write.68875950
Short name T408
Test name
Test status
Simulation time 2841440849 ps
CPU time 315.41 seconds
Started Jul 25 05:12:54 PM PDT 24
Finished Jul 25 05:18:09 PM PDT 24
Peak memory 236976 kb
Host smart-6f066062-1e3a-4062-bc81-2c7f46ae1286
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68875950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.68875950 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_burst_write/latest

Test location /workspace/coverage/default/10.kmac_edn_timeout_error.3406139296
Short name T940
Test name
Test status
Simulation time 79909213 ps
CPU time 0.9 seconds
Started Jul 25 05:12:53 PM PDT 24
Finished Jul 25 05:12:54 PM PDT 24
Peak memory 218236 kb
Host smart-d37574d5-0556-4a63-9124-8b0cc9d2be11
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3406139296 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.3406139296 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/10.kmac_entropy_mode_error.2310455636
Short name T1
Test name
Test status
Simulation time 2270769238 ps
CPU time 28.61 seconds
Started Jul 25 05:12:51 PM PDT 24
Finished Jul 25 05:13:19 PM PDT 24
Peak memory 226512 kb
Host smart-2962da53-40e4-4b36-b896-ca150e4c6a85
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2310455636 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.2310455636 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/10.kmac_entropy_refresh.2003478021
Short name T18
Test name
Test status
Simulation time 38705979564 ps
CPU time 270.57 seconds
Started Jul 25 05:12:53 PM PDT 24
Finished Jul 25 05:17:23 PM PDT 24
Peak memory 244168 kb
Host smart-2720d45f-318c-400c-961a-ffee64ff4db2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003478021 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.2
003478021 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/10.kmac_error.2842407381
Short name T457
Test name
Test status
Simulation time 2814883592 ps
CPU time 70.63 seconds
Started Jul 25 05:12:53 PM PDT 24
Finished Jul 25 05:14:03 PM PDT 24
Peak memory 243080 kb
Host smart-777e1550-49c4-4adf-9140-1d53ef37fe59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842407381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.2842407381 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_error/latest

Test location /workspace/coverage/default/10.kmac_key_error.1286456017
Short name T885
Test name
Test status
Simulation time 533430030 ps
CPU time 4.57 seconds
Started Jul 25 05:12:53 PM PDT 24
Finished Jul 25 05:12:58 PM PDT 24
Peak memory 223000 kb
Host smart-163523a2-ef5b-4675-8d89-1eecbf5511fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286456017 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.1286456017 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_key_error/latest

Test location /workspace/coverage/default/10.kmac_long_msg_and_output.4037524862
Short name T275
Test name
Test status
Simulation time 131076815441 ps
CPU time 1067.04 seconds
Started Jul 25 05:12:51 PM PDT 24
Finished Jul 25 05:30:38 PM PDT 24
Peak memory 322512 kb
Host smart-84aaaac1-0318-450b-88d5-433816280edc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037524862 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_a
nd_output.4037524862 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/10.kmac_sideload.794804306
Short name T224
Test name
Test status
Simulation time 31887609755 ps
CPU time 505.19 seconds
Started Jul 25 05:12:55 PM PDT 24
Finished Jul 25 05:21:20 PM PDT 24
Peak memory 256812 kb
Host smart-87488bd1-9d97-4af4-8a7e-d328ed714714
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794804306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.794804306 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_sideload/latest

Test location /workspace/coverage/default/10.kmac_smoke.975412330
Short name T244
Test name
Test status
Simulation time 2944313971 ps
CPU time 55.43 seconds
Started Jul 25 05:12:49 PM PDT 24
Finished Jul 25 05:13:44 PM PDT 24
Peak memory 226612 kb
Host smart-e30c934f-4707-4526-915a-9fc9b1bf20a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975412330 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.975412330 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_smoke/latest

Test location /workspace/coverage/default/10.kmac_stress_all.348448547
Short name T65
Test name
Test status
Simulation time 130073033207 ps
CPU time 1209.43 seconds
Started Jul 25 05:13:04 PM PDT 24
Finished Jul 25 05:33:13 PM PDT 24
Peak memory 354000 kb
Host smart-da760c21-5d0c-41fd-bd02-854b1c91ad9a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=348448547 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.348448547 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_stress_all/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_kmac.554762750
Short name T671
Test name
Test status
Simulation time 4800626039 ps
CPU time 8.27 seconds
Started Jul 25 05:12:51 PM PDT 24
Finished Jul 25 05:13:00 PM PDT 24
Peak memory 218688 kb
Host smart-21184d8f-e352-4e96-94cd-7777f1b0280c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554762750 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.kmac_test_vectors_kmac.554762750 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_kmac_xof.862044531
Short name T216
Test name
Test status
Simulation time 261375073 ps
CPU time 6.31 seconds
Started Jul 25 05:12:53 PM PDT 24
Finished Jul 25 05:12:59 PM PDT 24
Peak memory 219476 kb
Host smart-68b3f12d-434c-47e6-8d80-5b62d2a11b55
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862044531 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.kmac_test_vectors_kmac_xof.862044531 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_224.2954702767
Short name T759
Test name
Test status
Simulation time 1409996600729 ps
CPU time 2886.11 seconds
Started Jul 25 05:13:02 PM PDT 24
Finished Jul 25 06:01:09 PM PDT 24
Peak memory 404352 kb
Host smart-6e3d2eb8-7470-4554-a669-fc2d307b7e8c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2954702767 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_224.2954702767 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_256.906068014
Short name T489
Test name
Test status
Simulation time 92664054234 ps
CPU time 2206.54 seconds
Started Jul 25 05:12:52 PM PDT 24
Finished Jul 25 05:49:39 PM PDT 24
Peak memory 382956 kb
Host smart-4d50fb0a-5dec-4cf7-be0c-809fb5b36573
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=906068014 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_256.906068014 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_384.688301015
Short name T267
Test name
Test status
Simulation time 33251367501 ps
CPU time 1445.47 seconds
Started Jul 25 05:12:51 PM PDT 24
Finished Jul 25 05:36:56 PM PDT 24
Peak memory 338452 kb
Host smart-48d458a6-6179-4a44-81f4-27c03544a1a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=688301015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_384.688301015 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_512.1011281765
Short name T349
Test name
Test status
Simulation time 33253224791 ps
CPU time 1228.86 seconds
Started Jul 25 05:12:50 PM PDT 24
Finished Jul 25 05:33:19 PM PDT 24
Peak memory 300892 kb
Host smart-1d155d64-29c3-4919-bed8-a79d3df562ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1011281765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_512.1011281765 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_shake_128.3784449903
Short name T530
Test name
Test status
Simulation time 157156578862 ps
CPU time 5116.62 seconds
Started Jul 25 05:13:02 PM PDT 24
Finished Jul 25 06:38:20 PM PDT 24
Peak memory 645104 kb
Host smart-3daf74cf-3d36-4611-9edb-51278edfcece
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3784449903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_128.3784449903 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_shake_256.4067267630
Short name T716
Test name
Test status
Simulation time 464468080386 ps
CPU time 4643.84 seconds
Started Jul 25 05:13:02 PM PDT 24
Finished Jul 25 06:30:27 PM PDT 24
Peak memory 559896 kb
Host smart-488d607b-8659-4485-9431-8d2ea591f560
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4067267630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_256.4067267630 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/11.kmac_alert_test.536378157
Short name T774
Test name
Test status
Simulation time 129655870 ps
CPU time 0.83 seconds
Started Jul 25 05:13:07 PM PDT 24
Finished Jul 25 05:13:08 PM PDT 24
Peak memory 218240 kb
Host smart-a4a103ab-782d-4917-b55e-056ece96dfda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536378157 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.536378157 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/11.kmac_alert_test/latest

Test location /workspace/coverage/default/11.kmac_app.1101116198
Short name T647
Test name
Test status
Simulation time 6099172139 ps
CPU time 360.36 seconds
Started Jul 25 05:14:56 PM PDT 24
Finished Jul 25 05:20:56 PM PDT 24
Peak memory 250620 kb
Host smart-3d5cfa18-e067-44e9-b8e0-d0647e6298bd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101116198 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.1101116198 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/11.kmac_app/latest

Test location /workspace/coverage/default/11.kmac_burst_write.1468667379
Short name T510
Test name
Test status
Simulation time 18873260559 ps
CPU time 931.27 seconds
Started Jul 25 05:13:02 PM PDT 24
Finished Jul 25 05:28:34 PM PDT 24
Peak memory 235892 kb
Host smart-462cc030-1fe4-4703-a6b3-edf0808ddd4e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468667379 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.146866737
9 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_burst_write/latest

Test location /workspace/coverage/default/11.kmac_edn_timeout_error.3318476344
Short name T235
Test name
Test status
Simulation time 1395105190 ps
CPU time 8.91 seconds
Started Jul 25 05:13:01 PM PDT 24
Finished Jul 25 05:13:10 PM PDT 24
Peak memory 228196 kb
Host smart-71bab066-c0e9-4f00-9e73-be89a6c85463
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3318476344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.3318476344 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/11.kmac_entropy_mode_error.2208883494
Short name T441
Test name
Test status
Simulation time 92841218 ps
CPU time 6.01 seconds
Started Jul 25 05:13:02 PM PDT 24
Finished Jul 25 05:13:08 PM PDT 24
Peak memory 226524 kb
Host smart-fa24494a-c69a-4a90-8cfc-b3693b7e2db3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2208883494 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.2208883494 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/11.kmac_entropy_refresh.4125715861
Short name T949
Test name
Test status
Simulation time 30990264283 ps
CPU time 41.5 seconds
Started Jul 25 05:13:05 PM PDT 24
Finished Jul 25 05:13:46 PM PDT 24
Peak memory 227032 kb
Host smart-373f55be-ca4e-431c-86af-c8b8ad8f86a0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125715861 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.4
125715861 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/11.kmac_error.482618360
Short name T483
Test name
Test status
Simulation time 4614889601 ps
CPU time 188.94 seconds
Started Jul 25 05:13:07 PM PDT 24
Finished Jul 25 05:16:16 PM PDT 24
Peak memory 255056 kb
Host smart-f51a0582-3d6d-48f0-8c64-87a3b310eeb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482618360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.482618360 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_error/latest

Test location /workspace/coverage/default/11.kmac_key_error.1058092925
Short name T515
Test name
Test status
Simulation time 3668622160 ps
CPU time 13.23 seconds
Started Jul 25 05:13:04 PM PDT 24
Finished Jul 25 05:13:18 PM PDT 24
Peak memory 224812 kb
Host smart-6c7f1634-05ba-45f2-8d90-26d5b2e687e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058092925 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.1058092925 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_key_error/latest

Test location /workspace/coverage/default/11.kmac_lc_escalation.441764100
Short name T56
Test name
Test status
Simulation time 227337855 ps
CPU time 1.56 seconds
Started Jul 25 05:13:04 PM PDT 24
Finished Jul 25 05:13:06 PM PDT 24
Peak memory 226572 kb
Host smart-75e1f54d-a2c8-4526-877b-97a861d6fb2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441764100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.441764100 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/11.kmac_lc_escalation/latest

Test location /workspace/coverage/default/11.kmac_long_msg_and_output.540194117
Short name T233
Test name
Test status
Simulation time 37424337642 ps
CPU time 1228.76 seconds
Started Jul 25 05:13:08 PM PDT 24
Finished Jul 25 05:33:37 PM PDT 24
Peak memory 324748 kb
Host smart-c7b1fa85-9cc4-4fbf-ba63-a206ec24b31d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540194117 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_an
d_output.540194117 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/11.kmac_sideload.3450041280
Short name T430
Test name
Test status
Simulation time 1193458553 ps
CPU time 102.69 seconds
Started Jul 25 05:13:03 PM PDT 24
Finished Jul 25 05:14:46 PM PDT 24
Peak memory 231604 kb
Host smart-ec1a1477-623f-41be-ba6d-65b781ceba0a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450041280 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.3450041280 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_sideload/latest

Test location /workspace/coverage/default/11.kmac_smoke.4174431402
Short name T705
Test name
Test status
Simulation time 2000189086 ps
CPU time 68.92 seconds
Started Jul 25 05:13:00 PM PDT 24
Finished Jul 25 05:14:09 PM PDT 24
Peak memory 219436 kb
Host smart-62af577c-0d1c-4a43-bb85-0e2e882b1eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174431402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.4174431402 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_smoke/latest

Test location /workspace/coverage/default/11.kmac_stress_all.1431763727
Short name T536
Test name
Test status
Simulation time 20928655493 ps
CPU time 651.38 seconds
Started Jul 25 05:13:01 PM PDT 24
Finished Jul 25 05:23:53 PM PDT 24
Peak memory 309868 kb
Host smart-c69fae97-a869-46c9-b247-3a3707d9fe09
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1431763727 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.1431763727 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_stress_all/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_kmac.3746863327
Short name T910
Test name
Test status
Simulation time 217788584 ps
CPU time 5.46 seconds
Started Jul 25 05:13:02 PM PDT 24
Finished Jul 25 05:13:08 PM PDT 24
Peak memory 219464 kb
Host smart-1ab6218d-a753-4719-9054-b33abd4b91e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746863327 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.kmac_test_vectors_kmac.3746863327 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_kmac_xof.294244521
Short name T690
Test name
Test status
Simulation time 723324360 ps
CPU time 5.95 seconds
Started Jul 25 05:13:02 PM PDT 24
Finished Jul 25 05:13:08 PM PDT 24
Peak memory 218580 kb
Host smart-407bc5b5-804a-4734-b7c4-7e5beec89e9b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294244521 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.kmac_test_vectors_kmac_xof.294244521 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_224.1688347713
Short name T627
Test name
Test status
Simulation time 44930703156 ps
CPU time 1984.1 seconds
Started Jul 25 05:13:02 PM PDT 24
Finished Jul 25 05:46:07 PM PDT 24
Peak memory 391788 kb
Host smart-4706a989-4101-4cec-bc84-520238163a47
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1688347713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_224.1688347713 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_256.1099770584
Short name T353
Test name
Test status
Simulation time 63133437488 ps
CPU time 2067.81 seconds
Started Jul 25 05:13:03 PM PDT 24
Finished Jul 25 05:47:31 PM PDT 24
Peak memory 380952 kb
Host smart-6632787f-32be-467f-a947-0db33b21adc9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1099770584 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_256.1099770584 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_384.3633127441
Short name T661
Test name
Test status
Simulation time 259039627525 ps
CPU time 1674.37 seconds
Started Jul 25 05:13:05 PM PDT 24
Finished Jul 25 05:41:00 PM PDT 24
Peak memory 333624 kb
Host smart-b4d75feb-cdfb-4d67-acfc-8245c4b37aa4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3633127441 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_384.3633127441 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_512.4087987484
Short name T243
Test name
Test status
Simulation time 41893296790 ps
CPU time 1168.99 seconds
Started Jul 25 05:13:01 PM PDT 24
Finished Jul 25 05:32:30 PM PDT 24
Peak memory 301028 kb
Host smart-4bde041c-df63-4540-ad86-ecb9ef8b1184
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4087987484 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_512.4087987484 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_shake_128.1560909725
Short name T814
Test name
Test status
Simulation time 539128704320 ps
CPU time 5589.84 seconds
Started Jul 25 05:13:01 PM PDT 24
Finished Jul 25 06:46:12 PM PDT 24
Peak memory 657772 kb
Host smart-cca75548-9c24-4c8c-9773-febcf9ffc4be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1560909725 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_128.1560909725 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_shake_256.811735626
Short name T1045
Test name
Test status
Simulation time 220461387691 ps
CPU time 4761.17 seconds
Started Jul 25 05:13:08 PM PDT 24
Finished Jul 25 06:32:30 PM PDT 24
Peak memory 573600 kb
Host smart-23edf223-4346-4725-8059-3d774553d85c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=811735626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_256.811735626 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/12.kmac_alert_test.2982433110
Short name T593
Test name
Test status
Simulation time 22385980 ps
CPU time 0.79 seconds
Started Jul 25 05:13:14 PM PDT 24
Finished Jul 25 05:13:15 PM PDT 24
Peak memory 218280 kb
Host smart-fc121e5c-5ed8-447f-b71c-187f9f471ed3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982433110 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.2982433110 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_alert_test/latest

Test location /workspace/coverage/default/12.kmac_app.2544787912
Short name T877
Test name
Test status
Simulation time 8906764193 ps
CPU time 282.42 seconds
Started Jul 25 05:13:13 PM PDT 24
Finished Jul 25 05:17:56 PM PDT 24
Peak memory 249936 kb
Host smart-40b4ec27-868b-49ae-b091-2cd62444eb3b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544787912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.2544787912 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/12.kmac_app/latest

Test location /workspace/coverage/default/12.kmac_burst_write.2203537430
Short name T917
Test name
Test status
Simulation time 74175696112 ps
CPU time 1344.16 seconds
Started Jul 25 05:13:02 PM PDT 24
Finished Jul 25 05:35:27 PM PDT 24
Peak memory 238528 kb
Host smart-e38431f7-a687-41f1-b895-a7a0f5025dbc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203537430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.220353743
0 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_burst_write/latest

Test location /workspace/coverage/default/12.kmac_edn_timeout_error.1887634220
Short name T928
Test name
Test status
Simulation time 92637460 ps
CPU time 4.64 seconds
Started Jul 25 05:13:14 PM PDT 24
Finished Jul 25 05:13:19 PM PDT 24
Peak memory 225904 kb
Host smart-ad606d55-218f-4d79-acdd-27a67043f501
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1887634220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.1887634220 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/12.kmac_entropy_mode_error.2380465424
Short name T654
Test name
Test status
Simulation time 36227804 ps
CPU time 0.86 seconds
Started Jul 25 05:13:13 PM PDT 24
Finished Jul 25 05:13:14 PM PDT 24
Peak memory 220572 kb
Host smart-6c311170-0174-400e-bdae-410a88d6de00
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2380465424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.2380465424 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/12.kmac_entropy_refresh.3743456503
Short name T82
Test name
Test status
Simulation time 12767708208 ps
CPU time 370.29 seconds
Started Jul 25 05:13:12 PM PDT 24
Finished Jul 25 05:19:23 PM PDT 24
Peak memory 250356 kb
Host smart-718d66b1-5f29-485a-85d5-e98a2a3b9064
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743456503 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.3
743456503 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/12.kmac_key_error.3618788668
Short name T813
Test name
Test status
Simulation time 1051438345 ps
CPU time 9.1 seconds
Started Jul 25 05:13:13 PM PDT 24
Finished Jul 25 05:13:22 PM PDT 24
Peak memory 224408 kb
Host smart-e39f8c8d-fdea-43b7-8fbd-3093a4cf4e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618788668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.3618788668 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_key_error/latest

Test location /workspace/coverage/default/12.kmac_lc_escalation.2219965012
Short name T958
Test name
Test status
Simulation time 25497754 ps
CPU time 1.18 seconds
Started Jul 25 05:13:16 PM PDT 24
Finished Jul 25 05:13:17 PM PDT 24
Peak memory 226624 kb
Host smart-98af4f79-0ff8-4715-9700-babbdcf7a6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219965012 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.2219965012 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/12.kmac_lc_escalation/latest

Test location /workspace/coverage/default/12.kmac_long_msg_and_output.613194589
Short name T831
Test name
Test status
Simulation time 561704232 ps
CPU time 18.23 seconds
Started Jul 25 05:13:05 PM PDT 24
Finished Jul 25 05:13:23 PM PDT 24
Peak memory 221608 kb
Host smart-dfffd49f-510b-4f41-86a8-e3fe39ace0e1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613194589 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_an
d_output.613194589 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/12.kmac_sideload.3631749931
Short name T851
Test name
Test status
Simulation time 47992423333 ps
CPU time 503.7 seconds
Started Jul 25 05:13:02 PM PDT 24
Finished Jul 25 05:21:26 PM PDT 24
Peak memory 259460 kb
Host smart-739b0b94-7662-435a-aacf-ed6a4113c76c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631749931 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.3631749931 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_sideload/latest

Test location /workspace/coverage/default/12.kmac_smoke.1651583342
Short name T234
Test name
Test status
Simulation time 3672259521 ps
CPU time 76.88 seconds
Started Jul 25 05:13:03 PM PDT 24
Finished Jul 25 05:14:20 PM PDT 24
Peak memory 218592 kb
Host smart-99a081f6-10e9-4392-9622-d82609a082ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651583342 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.1651583342 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_smoke/latest

Test location /workspace/coverage/default/12.kmac_stress_all.2068558427
Short name T16
Test name
Test status
Simulation time 4888856275 ps
CPU time 373.61 seconds
Started Jul 25 05:13:14 PM PDT 24
Finished Jul 25 05:19:28 PM PDT 24
Peak memory 259668 kb
Host smart-110fefd2-8b89-4114-adc0-0d9d5470ef0e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2068558427 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.2068558427 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_stress_all/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_kmac.3561448257
Short name T843
Test name
Test status
Simulation time 789401893 ps
CPU time 5.86 seconds
Started Jul 25 05:13:12 PM PDT 24
Finished Jul 25 05:13:18 PM PDT 24
Peak memory 218536 kb
Host smart-9233fca6-418f-49a8-9f43-a401f424eac5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561448257 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.kmac_test_vectors_kmac.3561448257 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_kmac_xof.1023896065
Short name T1030
Test name
Test status
Simulation time 272679869 ps
CPU time 6.4 seconds
Started Jul 25 05:13:13 PM PDT 24
Finished Jul 25 05:13:20 PM PDT 24
Peak memory 218552 kb
Host smart-13cab7a9-20a6-4692-8eb3-4f06db0aca3f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023896065 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.kmac_test_vectors_kmac_xof.1023896065 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_224.920268057
Short name T562
Test name
Test status
Simulation time 935982461270 ps
CPU time 2638.46 seconds
Started Jul 25 05:13:02 PM PDT 24
Finished Jul 25 05:57:01 PM PDT 24
Peak memory 395620 kb
Host smart-5fbf3c7e-3077-4219-b046-e8b5c36ba2f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=920268057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_224.920268057 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_256.3545719325
Short name T614
Test name
Test status
Simulation time 85044716871 ps
CPU time 2033.77 seconds
Started Jul 25 05:13:13 PM PDT 24
Finished Jul 25 05:47:07 PM PDT 24
Peak memory 387980 kb
Host smart-0ef1a79a-76ff-4b80-93e4-422456f231fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3545719325 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_256.3545719325 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_384.1389889945
Short name T836
Test name
Test status
Simulation time 60351193697 ps
CPU time 1630.59 seconds
Started Jul 25 05:13:14 PM PDT 24
Finished Jul 25 05:40:25 PM PDT 24
Peak memory 341392 kb
Host smart-60a26ad2-235a-4417-9d01-0e2396e6cb5a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1389889945 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_384.1389889945 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_512.1010934116
Short name T220
Test name
Test status
Simulation time 208963605418 ps
CPU time 1320.12 seconds
Started Jul 25 05:13:11 PM PDT 24
Finished Jul 25 05:35:12 PM PDT 24
Peak memory 299308 kb
Host smart-a27cb97a-e40d-45cd-9d6d-dfa63d21806d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1010934116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_512.1010934116 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_shake_128.2620936543
Short name T818
Test name
Test status
Simulation time 61890880444 ps
CPU time 5473.07 seconds
Started Jul 25 05:13:14 PM PDT 24
Finished Jul 25 06:44:28 PM PDT 24
Peak memory 659932 kb
Host smart-39cda429-18f3-4016-a687-91e39efe39e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2620936543 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_128.2620936543 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_shake_256.681475424
Short name T418
Test name
Test status
Simulation time 202459378451 ps
CPU time 4950.97 seconds
Started Jul 25 05:13:15 PM PDT 24
Finished Jul 25 06:35:46 PM PDT 24
Peak memory 558368 kb
Host smart-d5e79481-ee5a-4086-b0db-493d45303c84
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=681475424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_256.681475424 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/13.kmac_app.2581748443
Short name T110
Test name
Test status
Simulation time 24638141078 ps
CPU time 180.91 seconds
Started Jul 25 05:13:13 PM PDT 24
Finished Jul 25 05:16:14 PM PDT 24
Peak memory 239864 kb
Host smart-b0334f2e-dee4-4984-9ab3-5babf79ffac4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581748443 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.2581748443 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/13.kmac_app/latest

Test location /workspace/coverage/default/13.kmac_burst_write.3763620752
Short name T603
Test name
Test status
Simulation time 1704724385 ps
CPU time 54.62 seconds
Started Jul 25 05:13:14 PM PDT 24
Finished Jul 25 05:14:09 PM PDT 24
Peak memory 226596 kb
Host smart-a99164c3-ba99-4a2d-b43e-7a198d54a962
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763620752 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.376362075
2 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_burst_write/latest

Test location /workspace/coverage/default/13.kmac_edn_timeout_error.2187979512
Short name T738
Test name
Test status
Simulation time 17992461 ps
CPU time 0.91 seconds
Started Jul 25 05:13:13 PM PDT 24
Finished Jul 25 05:13:14 PM PDT 24
Peak memory 218320 kb
Host smart-2ea463e0-9550-4526-8ac3-8fb89cb0705a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2187979512 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.2187979512 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_mode_error.2369894057
Short name T104
Test name
Test status
Simulation time 10984608 ps
CPU time 0.83 seconds
Started Jul 25 05:13:11 PM PDT 24
Finished Jul 25 05:13:12 PM PDT 24
Peak memory 220260 kb
Host smart-3c6e4078-6d1b-4c21-8a8b-4a7dcd89699c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2369894057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.2369894057 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_refresh.878160892
Short name T535
Test name
Test status
Simulation time 29206506266 ps
CPU time 266.03 seconds
Started Jul 25 05:13:13 PM PDT 24
Finished Jul 25 05:17:39 PM PDT 24
Peak memory 246680 kb
Host smart-450a297c-3fcd-4ea4-b103-8c0068ef6fb7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878160892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.87
8160892 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/13.kmac_error.414418440
Short name T607
Test name
Test status
Simulation time 3298458867 ps
CPU time 102.4 seconds
Started Jul 25 05:13:13 PM PDT 24
Finished Jul 25 05:14:55 PM PDT 24
Peak memory 242452 kb
Host smart-a199bd81-8a3f-444a-ac37-ae8791fdee2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414418440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.414418440 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_error/latest

Test location /workspace/coverage/default/13.kmac_key_error.2370826734
Short name T4
Test name
Test status
Simulation time 6273935257 ps
CPU time 8.01 seconds
Started Jul 25 05:13:13 PM PDT 24
Finished Jul 25 05:13:21 PM PDT 24
Peak memory 223616 kb
Host smart-4a6ea90f-b60c-4b1f-a66b-9894965b81e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370826734 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.2370826734 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_key_error/latest

Test location /workspace/coverage/default/13.kmac_lc_escalation.3732826012
Short name T13
Test name
Test status
Simulation time 180761906 ps
CPU time 1.38 seconds
Started Jul 25 05:13:14 PM PDT 24
Finished Jul 25 05:13:15 PM PDT 24
Peak memory 226500 kb
Host smart-a7f4f314-72b9-4074-a3b1-18cd7a220d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732826012 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.3732826012 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/13.kmac_lc_escalation/latest

Test location /workspace/coverage/default/13.kmac_long_msg_and_output.730697742
Short name T859
Test name
Test status
Simulation time 327158172626 ps
CPU time 2971.27 seconds
Started Jul 25 05:13:13 PM PDT 24
Finished Jul 25 06:02:45 PM PDT 24
Peak memory 471716 kb
Host smart-462c56af-ebe4-4e4c-ad98-38cdb5fafd44
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730697742 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_an
d_output.730697742 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/13.kmac_sideload.28087323
Short name T1070
Test name
Test status
Simulation time 27064768987 ps
CPU time 212.92 seconds
Started Jul 25 05:13:14 PM PDT 24
Finished Jul 25 05:16:47 PM PDT 24
Peak memory 240612 kb
Host smart-e68b7465-4bbc-4cf4-8e7f-f2a95e21f5db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28087323 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.28087323 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_sideload/latest

Test location /workspace/coverage/default/13.kmac_smoke.3508265265
Short name T422
Test name
Test status
Simulation time 9990144509 ps
CPU time 64.96 seconds
Started Jul 25 05:13:13 PM PDT 24
Finished Jul 25 05:14:19 PM PDT 24
Peak memory 221256 kb
Host smart-1c7457df-f6bb-47cf-a20b-3fa5bd66c2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508265265 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.3508265265 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_smoke/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_kmac.1067137335
Short name T953
Test name
Test status
Simulation time 274057912 ps
CPU time 6.07 seconds
Started Jul 25 05:13:15 PM PDT 24
Finished Jul 25 05:13:21 PM PDT 24
Peak memory 218560 kb
Host smart-af3dd520-9a3b-439a-ac5f-d3f6d4eae57a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067137335 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.kmac_test_vectors_kmac.1067137335 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_kmac_xof.3615939425
Short name T212
Test name
Test status
Simulation time 484656541 ps
CPU time 6.01 seconds
Started Jul 25 05:13:12 PM PDT 24
Finished Jul 25 05:13:18 PM PDT 24
Peak memory 218564 kb
Host smart-35320ecb-f1b4-4ef9-addb-1d1b73d99333
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615939425 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.kmac_test_vectors_kmac_xof.3615939425 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_224.591153830
Short name T795
Test name
Test status
Simulation time 358885351547 ps
CPU time 2412.39 seconds
Started Jul 25 05:13:12 PM PDT 24
Finished Jul 25 05:53:25 PM PDT 24
Peak memory 396300 kb
Host smart-bd75238d-3f8a-4d63-85a1-de39daa91426
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=591153830 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_224.591153830 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_256.2807088938
Short name T307
Test name
Test status
Simulation time 125788254240 ps
CPU time 2109.2 seconds
Started Jul 25 05:13:16 PM PDT 24
Finished Jul 25 05:48:26 PM PDT 24
Peak memory 383860 kb
Host smart-ee97ede3-50b0-4d2d-a0b1-cd435bf84b28
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2807088938 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_256.2807088938 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_384.528484385
Short name T808
Test name
Test status
Simulation time 137023256218 ps
CPU time 1731.94 seconds
Started Jul 25 05:13:15 PM PDT 24
Finished Jul 25 05:42:07 PM PDT 24
Peak memory 345240 kb
Host smart-fd7c26a8-aa6c-4e70-810a-11f14afdcdc9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=528484385 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_384.528484385 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_512.3182019740
Short name T263
Test name
Test status
Simulation time 547994573893 ps
CPU time 1582.76 seconds
Started Jul 25 05:13:14 PM PDT 24
Finished Jul 25 05:39:37 PM PDT 24
Peak memory 301308 kb
Host smart-61c779f6-8bf2-47b1-9741-a30d8af039ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3182019740 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_512.3182019740 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_shake_128.803010320
Short name T595
Test name
Test status
Simulation time 60718896634 ps
CPU time 5111.94 seconds
Started Jul 25 05:13:11 PM PDT 24
Finished Jul 25 06:38:24 PM PDT 24
Peak memory 655516 kb
Host smart-5948e057-b5ee-4acc-9b96-47a88aed8726
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=803010320 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_128.803010320 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_shake_256.2224970373
Short name T416
Test name
Test status
Simulation time 215965179583 ps
CPU time 5063.6 seconds
Started Jul 25 05:13:12 PM PDT 24
Finished Jul 25 06:37:36 PM PDT 24
Peak memory 559184 kb
Host smart-be78fbc7-d93b-49f8-a4bf-bb8219beec53
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2224970373 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_256.2224970373 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/14.kmac_alert_test.879118715
Short name T113
Test name
Test status
Simulation time 51922564 ps
CPU time 0.83 seconds
Started Jul 25 05:13:26 PM PDT 24
Finished Jul 25 05:13:27 PM PDT 24
Peak memory 218368 kb
Host smart-fc925213-8d51-4149-b4e1-557e432a1593
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879118715 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.879118715 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/14.kmac_alert_test/latest

Test location /workspace/coverage/default/14.kmac_app.856975531
Short name T451
Test name
Test status
Simulation time 40664106158 ps
CPU time 319.69 seconds
Started Jul 25 05:13:25 PM PDT 24
Finished Jul 25 05:18:45 PM PDT 24
Peak memory 248932 kb
Host smart-d3b114db-5660-42dc-8351-7684c7545f68
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856975531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.856975531 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/14.kmac_app/latest

Test location /workspace/coverage/default/14.kmac_burst_write.986670783
Short name T123
Test name
Test status
Simulation time 1323208537 ps
CPU time 119.81 seconds
Started Jul 25 05:13:24 PM PDT 24
Finished Jul 25 05:15:24 PM PDT 24
Peak memory 226556 kb
Host smart-5a6044ae-d412-44a1-a0c0-785573e7b537
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986670783 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.986670783
+enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_burst_write/latest

Test location /workspace/coverage/default/14.kmac_edn_timeout_error.3732233939
Short name T789
Test name
Test status
Simulation time 24124211 ps
CPU time 1.13 seconds
Started Jul 25 05:13:26 PM PDT 24
Finished Jul 25 05:13:27 PM PDT 24
Peak memory 218328 kb
Host smart-4fc7c51e-a57d-40a7-9b5b-57ffe4ef83b5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3732233939 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.3732233939 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/14.kmac_entropy_mode_error.1952052005
Short name T44
Test name
Test status
Simulation time 190501847 ps
CPU time 0.95 seconds
Started Jul 25 05:13:25 PM PDT 24
Finished Jul 25 05:13:26 PM PDT 24
Peak memory 218280 kb
Host smart-b5d7e105-8c24-4155-af92-f17faad723d0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1952052005 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.1952052005 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/14.kmac_entropy_refresh.4046809637
Short name T77
Test name
Test status
Simulation time 9044740479 ps
CPU time 192.92 seconds
Started Jul 25 05:13:25 PM PDT 24
Finished Jul 25 05:16:38 PM PDT 24
Peak memory 240856 kb
Host smart-f4c40e0a-87e6-4fd5-a1fc-b04e3b892048
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046809637 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.4
046809637 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/14.kmac_error.463616256
Short name T51
Test name
Test status
Simulation time 5918850114 ps
CPU time 523.84 seconds
Started Jul 25 05:13:27 PM PDT 24
Finished Jul 25 05:22:11 PM PDT 24
Peak memory 269168 kb
Host smart-805319fa-00d2-456a-8d06-a6b6c1b4280c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463616256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.463616256 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_error/latest

Test location /workspace/coverage/default/14.kmac_key_error.3393465199
Short name T345
Test name
Test status
Simulation time 61330352 ps
CPU time 1.21 seconds
Started Jul 25 05:13:26 PM PDT 24
Finished Jul 25 05:13:27 PM PDT 24
Peak memory 222028 kb
Host smart-6e9b7e6e-2a2f-4cc8-8215-69174e24d79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393465199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.3393465199 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_key_error/latest

Test location /workspace/coverage/default/14.kmac_long_msg_and_output.2664018401
Short name T974
Test name
Test status
Simulation time 34849969515 ps
CPU time 264.84 seconds
Started Jul 25 05:13:25 PM PDT 24
Finished Jul 25 05:17:50 PM PDT 24
Peak memory 244276 kb
Host smart-c1fc09a4-8c5f-42a1-b4f8-daf827f333c3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664018401 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_a
nd_output.2664018401 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/14.kmac_sideload.556127390
Short name T337
Test name
Test status
Simulation time 745905463 ps
CPU time 17.33 seconds
Started Jul 25 05:13:25 PM PDT 24
Finished Jul 25 05:13:43 PM PDT 24
Peak memory 220612 kb
Host smart-b8a7efab-ea72-45b3-b56f-3e4265b2d167
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556127390 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.556127390 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_sideload/latest

Test location /workspace/coverage/default/14.kmac_smoke.1715854340
Short name T922
Test name
Test status
Simulation time 2774618052 ps
CPU time 43.96 seconds
Started Jul 25 05:13:24 PM PDT 24
Finished Jul 25 05:14:08 PM PDT 24
Peak memory 226656 kb
Host smart-4674417a-3ad8-43c8-b85f-69d9ffe4acc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715854340 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.1715854340 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_smoke/latest

Test location /workspace/coverage/default/14.kmac_stress_all.3118256824
Short name T538
Test name
Test status
Simulation time 20944696227 ps
CPU time 1763.66 seconds
Started Jul 25 05:13:28 PM PDT 24
Finished Jul 25 05:42:52 PM PDT 24
Peak memory 431676 kb
Host smart-a7607c09-fbf0-4d14-9c1e-adee3b1d0a69
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3118256824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.3118256824 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_stress_all/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_kmac.96475946
Short name T609
Test name
Test status
Simulation time 655754275 ps
CPU time 6.3 seconds
Started Jul 25 05:13:26 PM PDT 24
Finished Jul 25 05:13:32 PM PDT 24
Peak memory 218628 kb
Host smart-e400e9a8-9458-44e1-bf34-053cdd5cdba5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96475946 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 14.kmac_test_vectors_kmac.96475946 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_kmac_xof.1559084457
Short name T713
Test name
Test status
Simulation time 403465339 ps
CPU time 6.59 seconds
Started Jul 25 05:13:26 PM PDT 24
Finished Jul 25 05:13:33 PM PDT 24
Peak memory 218696 kb
Host smart-9b70029a-a335-4bc1-b530-3d1a51fc8118
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559084457 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.kmac_test_vectors_kmac_xof.1559084457 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_224.606383156
Short name T567
Test name
Test status
Simulation time 88976317131 ps
CPU time 1939.5 seconds
Started Jul 25 05:13:28 PM PDT 24
Finished Jul 25 05:45:48 PM PDT 24
Peak memory 381508 kb
Host smart-fa2debac-c4b5-4ec1-9bdf-66ae0e1b6dc9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=606383156 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_224.606383156 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_256.1035740919
Short name T1019
Test name
Test status
Simulation time 92417385773 ps
CPU time 2287.05 seconds
Started Jul 25 05:13:25 PM PDT 24
Finished Jul 25 05:51:33 PM PDT 24
Peak memory 382448 kb
Host smart-0247ab73-59eb-4929-8ad2-316f5502e404
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1035740919 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_256.1035740919 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_384.2492337779
Short name T324
Test name
Test status
Simulation time 297086978264 ps
CPU time 1925.8 seconds
Started Jul 25 05:13:25 PM PDT 24
Finished Jul 25 05:45:31 PM PDT 24
Peak memory 341424 kb
Host smart-db8bed6e-c574-46bb-b550-f977bb4173c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2492337779 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_384.2492337779 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_512.846288546
Short name T526
Test name
Test status
Simulation time 137344138747 ps
CPU time 1272.93 seconds
Started Jul 25 05:13:26 PM PDT 24
Finished Jul 25 05:34:39 PM PDT 24
Peak memory 299580 kb
Host smart-7b0038a1-65f3-49b7-9b35-c6927124c59d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=846288546 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_512.846288546 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_shake_128.4247227204
Short name T553
Test name
Test status
Simulation time 240765296653 ps
CPU time 5202.04 seconds
Started Jul 25 05:13:25 PM PDT 24
Finished Jul 25 06:40:07 PM PDT 24
Peak memory 657540 kb
Host smart-b5abe0f8-9ba7-47e1-a745-3f60b6981ae3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4247227204 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_128.4247227204 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_shake_256.3065988804
Short name T410
Test name
Test status
Simulation time 883545888089 ps
CPU time 5332.24 seconds
Started Jul 25 05:13:27 PM PDT 24
Finished Jul 25 06:42:20 PM PDT 24
Peak memory 581812 kb
Host smart-e76b2b95-9f76-4b7d-b399-4164c9ec21f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3065988804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_256.3065988804 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/15.kmac_alert_test.239376718
Short name T1068
Test name
Test status
Simulation time 35367226 ps
CPU time 0.78 seconds
Started Jul 25 05:13:53 PM PDT 24
Finished Jul 25 05:13:54 PM PDT 24
Peak memory 218264 kb
Host smart-6a0f5d16-1005-4814-9fe2-f08a51f0031e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239376718 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.239376718 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/15.kmac_alert_test/latest

Test location /workspace/coverage/default/15.kmac_app.748907405
Short name T596
Test name
Test status
Simulation time 12157512436 ps
CPU time 99.74 seconds
Started Jul 25 05:13:29 PM PDT 24
Finished Jul 25 05:15:09 PM PDT 24
Peak memory 233100 kb
Host smart-2a41f225-e536-410b-90ae-b32684629746
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748907405 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.748907405 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/15.kmac_app/latest

Test location /workspace/coverage/default/15.kmac_burst_write.883458869
Short name T518
Test name
Test status
Simulation time 173926791452 ps
CPU time 935.03 seconds
Started Jul 25 05:13:27 PM PDT 24
Finished Jul 25 05:29:02 PM PDT 24
Peak memory 235724 kb
Host smart-4ab16e75-92fe-446c-aa6f-0998c258c0db
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883458869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.883458869
+enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_burst_write/latest

Test location /workspace/coverage/default/15.kmac_edn_timeout_error.1304693865
Short name T79
Test name
Test status
Simulation time 246450490 ps
CPU time 1.35 seconds
Started Jul 25 05:13:39 PM PDT 24
Finished Jul 25 05:13:41 PM PDT 24
Peak memory 218316 kb
Host smart-7c49f12c-fb19-43a8-99ef-fce132bfa309
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1304693865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.1304693865 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/15.kmac_entropy_mode_error.2172163799
Short name T85
Test name
Test status
Simulation time 20566185 ps
CPU time 1.16 seconds
Started Jul 25 05:13:37 PM PDT 24
Finished Jul 25 05:13:38 PM PDT 24
Peak memory 221744 kb
Host smart-b1327ee8-7a64-4844-ab91-69ab6940e6f9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2172163799 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.2172163799 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/15.kmac_entropy_refresh.3683524239
Short name T1060
Test name
Test status
Simulation time 13449473488 ps
CPU time 284.22 seconds
Started Jul 25 05:13:38 PM PDT 24
Finished Jul 25 05:18:22 PM PDT 24
Peak memory 248892 kb
Host smart-b9e5171b-b973-48ae-b9ed-9489884500fe
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683524239 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.3
683524239 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/15.kmac_error.3297827878
Short name T100
Test name
Test status
Simulation time 46014679059 ps
CPU time 314.21 seconds
Started Jul 25 05:13:38 PM PDT 24
Finished Jul 25 05:18:53 PM PDT 24
Peak memory 258780 kb
Host smart-9269f47a-e696-4b0a-8992-2e8125d78174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297827878 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.3297827878 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_error/latest

Test location /workspace/coverage/default/15.kmac_key_error.2397948415
Short name T684
Test name
Test status
Simulation time 2407076273 ps
CPU time 3.03 seconds
Started Jul 25 05:13:38 PM PDT 24
Finished Jul 25 05:13:41 PM PDT 24
Peak memory 222872 kb
Host smart-1de552ae-961a-42ad-acc6-d49af9c64ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397948415 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.2397948415 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_key_error/latest

Test location /workspace/coverage/default/15.kmac_lc_escalation.2845816197
Short name T557
Test name
Test status
Simulation time 276245937 ps
CPU time 1.32 seconds
Started Jul 25 05:13:39 PM PDT 24
Finished Jul 25 05:13:41 PM PDT 24
Peak memory 226540 kb
Host smart-dd0c553f-bfa7-4e70-be4b-babddddb81e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845816197 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.2845816197 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/15.kmac_lc_escalation/latest

Test location /workspace/coverage/default/15.kmac_long_msg_and_output.3661285601
Short name T900
Test name
Test status
Simulation time 132454843159 ps
CPU time 1066.58 seconds
Started Jul 25 05:13:26 PM PDT 24
Finished Jul 25 05:31:13 PM PDT 24
Peak memory 313696 kb
Host smart-5502e89f-eda5-4720-9150-301a1ac496b5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661285601 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_a
nd_output.3661285601 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/15.kmac_sideload.1802452543
Short name T1069
Test name
Test status
Simulation time 26351659397 ps
CPU time 71.98 seconds
Started Jul 25 05:13:26 PM PDT 24
Finished Jul 25 05:14:38 PM PDT 24
Peak memory 229820 kb
Host smart-d5c1acb8-63c6-4ae1-bbce-b111c5a022dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802452543 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.1802452543 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_sideload/latest

Test location /workspace/coverage/default/15.kmac_smoke.947848177
Short name T521
Test name
Test status
Simulation time 1590957014 ps
CPU time 14.76 seconds
Started Jul 25 05:13:27 PM PDT 24
Finished Jul 25 05:13:42 PM PDT 24
Peak memory 226240 kb
Host smart-80edfc5a-f693-47a7-96e9-3ad08e042e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947848177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.947848177 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_smoke/latest

Test location /workspace/coverage/default/15.kmac_stress_all.2509747234
Short name T325
Test name
Test status
Simulation time 40619483858 ps
CPU time 318.97 seconds
Started Jul 25 05:13:43 PM PDT 24
Finished Jul 25 05:19:02 PM PDT 24
Peak memory 267808 kb
Host smart-f2d1e4a8-3ab7-485f-bc22-60388fae0a0d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2509747234 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.2509747234 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_stress_all/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_kmac.3114331935
Short name T961
Test name
Test status
Simulation time 212813311 ps
CPU time 6.46 seconds
Started Jul 25 05:13:27 PM PDT 24
Finished Jul 25 05:13:34 PM PDT 24
Peak memory 218524 kb
Host smart-b761025d-6119-4bf9-a351-524c77c3b3f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114331935 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.kmac_test_vectors_kmac.3114331935 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_kmac_xof.3060458021
Short name T998
Test name
Test status
Simulation time 479763976 ps
CPU time 5.6 seconds
Started Jul 25 05:13:29 PM PDT 24
Finished Jul 25 05:13:35 PM PDT 24
Peak memory 218584 kb
Host smart-44e16039-8f1f-4587-9141-ad5b084ff5e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060458021 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.kmac_test_vectors_kmac_xof.3060458021 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_224.2748132036
Short name T973
Test name
Test status
Simulation time 150316115416 ps
CPU time 2202.84 seconds
Started Jul 25 05:13:27 PM PDT 24
Finished Jul 25 05:50:11 PM PDT 24
Peak memory 401028 kb
Host smart-a03dbea4-dbf1-430d-aede-b7da36ae443a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2748132036 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_224.2748132036 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_256.2799053594
Short name T1003
Test name
Test status
Simulation time 250559923990 ps
CPU time 2243.93 seconds
Started Jul 25 05:13:27 PM PDT 24
Finished Jul 25 05:50:51 PM PDT 24
Peak memory 390428 kb
Host smart-67cf40b8-5466-4a26-a603-0ccff29839ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2799053594 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_256.2799053594 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_384.812309261
Short name T573
Test name
Test status
Simulation time 223550859119 ps
CPU time 1729.76 seconds
Started Jul 25 05:13:27 PM PDT 24
Finished Jul 25 05:42:18 PM PDT 24
Peak memory 337288 kb
Host smart-e89b0dbd-f711-47a8-8392-4fb72deef1da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=812309261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_384.812309261 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_512.2175621125
Short name T897
Test name
Test status
Simulation time 20798685892 ps
CPU time 1085.92 seconds
Started Jul 25 05:13:25 PM PDT 24
Finished Jul 25 05:31:32 PM PDT 24
Peak memory 300284 kb
Host smart-cfee122f-f6e8-4d7f-a2eb-36c946d177c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2175621125 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_512.2175621125 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_shake_128.73266641
Short name T109
Test name
Test status
Simulation time 1034547473285 ps
CPU time 6339.84 seconds
Started Jul 25 05:13:29 PM PDT 24
Finished Jul 25 06:59:09 PM PDT 24
Peak memory 658624 kb
Host smart-0e0ece39-078b-432b-a3b8-6f15fe99f84f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=73266641 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_128.73266641 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_shake_256.3408122859
Short name T126
Test name
Test status
Simulation time 806848616567 ps
CPU time 4978.58 seconds
Started Jul 25 05:13:28 PM PDT 24
Finished Jul 25 06:36:27 PM PDT 24
Peak memory 576180 kb
Host smart-386a1e18-f817-47d1-8fd9-80f7cd1d71f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3408122859 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_256.3408122859 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/16.kmac_alert_test.2635714998
Short name T884
Test name
Test status
Simulation time 29540403 ps
CPU time 0.84 seconds
Started Jul 25 05:13:39 PM PDT 24
Finished Jul 25 05:13:40 PM PDT 24
Peak memory 218236 kb
Host smart-2be11111-f004-4464-b4ea-026db9cda464
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635714998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.2635714998 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_alert_test/latest

Test location /workspace/coverage/default/16.kmac_app.3871984851
Short name T825
Test name
Test status
Simulation time 476972618 ps
CPU time 29.23 seconds
Started Jul 25 05:13:36 PM PDT 24
Finished Jul 25 05:14:06 PM PDT 24
Peak memory 226652 kb
Host smart-98cac0d5-be43-47d9-9728-490b39dfc367
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871984851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.3871984851 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/16.kmac_app/latest

Test location /workspace/coverage/default/16.kmac_burst_write.3415249473
Short name T793
Test name
Test status
Simulation time 27064177999 ps
CPU time 942.15 seconds
Started Jul 25 05:13:41 PM PDT 24
Finished Jul 25 05:29:23 PM PDT 24
Peak memory 243064 kb
Host smart-e8a499cf-c371-49f3-9da2-73f1526087c0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415249473 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.341524947
3 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_burst_write/latest

Test location /workspace/coverage/default/16.kmac_edn_timeout_error.622779060
Short name T815
Test name
Test status
Simulation time 66509288 ps
CPU time 0.93 seconds
Started Jul 25 05:13:41 PM PDT 24
Finished Jul 25 05:13:42 PM PDT 24
Peak memory 218236 kb
Host smart-277473bd-e341-4b76-a4e1-1885d1888ff3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=622779060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.622779060 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_mode_error.3763829241
Short name T828
Test name
Test status
Simulation time 21703484 ps
CPU time 1.1 seconds
Started Jul 25 05:13:39 PM PDT 24
Finished Jul 25 05:13:41 PM PDT 24
Peak memory 221804 kb
Host smart-a9f4472d-08a5-4e61-ac10-fb77fc67577b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3763829241 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.3763829241 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_refresh.2068009258
Short name T420
Test name
Test status
Simulation time 5811602134 ps
CPU time 28.35 seconds
Started Jul 25 05:13:39 PM PDT 24
Finished Jul 25 05:14:08 PM PDT 24
Peak memory 240124 kb
Host smart-da3c3cc9-8808-48ee-9dcc-2d1454850f46
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068009258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.2
068009258 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/16.kmac_error.2046283956
Short name T845
Test name
Test status
Simulation time 10481673829 ps
CPU time 260.55 seconds
Started Jul 25 05:13:37 PM PDT 24
Finished Jul 25 05:17:58 PM PDT 24
Peak memory 251240 kb
Host smart-52fbf0fa-de64-419d-9759-b19cc8290820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046283956 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.2046283956 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_error/latest

Test location /workspace/coverage/default/16.kmac_key_error.1262230348
Short name T403
Test name
Test status
Simulation time 489022207 ps
CPU time 1.54 seconds
Started Jul 25 05:13:38 PM PDT 24
Finished Jul 25 05:13:40 PM PDT 24
Peak memory 222016 kb
Host smart-ebe5c37b-ef00-4550-96d4-6d4a5f7578fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262230348 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.1262230348 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_key_error/latest

Test location /workspace/coverage/default/16.kmac_lc_escalation.1034539141
Short name T54
Test name
Test status
Simulation time 48304515 ps
CPU time 1.42 seconds
Started Jul 25 05:13:40 PM PDT 24
Finished Jul 25 05:13:41 PM PDT 24
Peak memory 226616 kb
Host smart-bb9f8680-2d64-42ea-8407-1e1745c97a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034539141 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.1034539141 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/16.kmac_lc_escalation/latest

Test location /workspace/coverage/default/16.kmac_long_msg_and_output.1314035485
Short name T832
Test name
Test status
Simulation time 333017153806 ps
CPU time 2040.55 seconds
Started Jul 25 05:13:39 PM PDT 24
Finished Jul 25 05:47:40 PM PDT 24
Peak memory 378148 kb
Host smart-90763c01-6f51-4471-894a-0b24e21dde1f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314035485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_a
nd_output.1314035485 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/16.kmac_sideload.2370233351
Short name T532
Test name
Test status
Simulation time 5300444544 ps
CPU time 371.16 seconds
Started Jul 25 05:13:36 PM PDT 24
Finished Jul 25 05:19:47 PM PDT 24
Peak memory 249376 kb
Host smart-c53f20ff-6b6c-4698-8e20-32d762da0b4e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370233351 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.2370233351 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_sideload/latest

Test location /workspace/coverage/default/16.kmac_smoke.1032212167
Short name T67
Test name
Test status
Simulation time 1309012654 ps
CPU time 55.15 seconds
Started Jul 25 05:13:41 PM PDT 24
Finished Jul 25 05:14:36 PM PDT 24
Peak memory 222752 kb
Host smart-ec1b8747-2303-4b91-a0b9-3291aba775c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032212167 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.1032212167 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_smoke/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_kmac.3871453863
Short name T400
Test name
Test status
Simulation time 928102687 ps
CPU time 5.73 seconds
Started Jul 25 05:13:50 PM PDT 24
Finished Jul 25 05:13:56 PM PDT 24
Peak memory 218584 kb
Host smart-b597c40f-1796-48a3-8031-ecbc885faa11
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871453863 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.kmac_test_vectors_kmac.3871453863 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_kmac_xof.543582210
Short name T437
Test name
Test status
Simulation time 465010889 ps
CPU time 6.31 seconds
Started Jul 25 05:13:42 PM PDT 24
Finished Jul 25 05:13:49 PM PDT 24
Peak memory 219488 kb
Host smart-189df38e-06cf-4638-bf2b-e5a637a1389e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543582210 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.kmac_test_vectors_kmac_xof.543582210 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_224.3629464690
Short name T125
Test name
Test status
Simulation time 143891549735 ps
CPU time 2280.08 seconds
Started Jul 25 05:13:37 PM PDT 24
Finished Jul 25 05:51:37 PM PDT 24
Peak memory 400176 kb
Host smart-612001c0-98ff-4bc1-89d0-b75d7fb1ea2e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3629464690 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_224.3629464690 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_256.3487180366
Short name T291
Test name
Test status
Simulation time 39749891520 ps
CPU time 1968.1 seconds
Started Jul 25 05:13:40 PM PDT 24
Finished Jul 25 05:46:28 PM PDT 24
Peak memory 395444 kb
Host smart-f593eba8-3e66-41df-8e5f-ceb47ec92df6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3487180366 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_256.3487180366 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_384.4098712113
Short name T297
Test name
Test status
Simulation time 30482466679 ps
CPU time 1486.84 seconds
Started Jul 25 05:13:38 PM PDT 24
Finished Jul 25 05:38:25 PM PDT 24
Peak memory 343920 kb
Host smart-f305cfc2-9ea6-4ae7-8e96-148525c8401f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4098712113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_384.4098712113 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_512.1303366113
Short name T878
Test name
Test status
Simulation time 20875013370 ps
CPU time 1177.17 seconds
Started Jul 25 05:13:43 PM PDT 24
Finished Jul 25 05:33:21 PM PDT 24
Peak memory 299544 kb
Host smart-4be6059c-56d2-427c-9813-3b4eb50c0e76
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1303366113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_512.1303366113 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_shake_128.3604315487
Short name T610
Test name
Test status
Simulation time 685435703539 ps
CPU time 5513.41 seconds
Started Jul 25 05:13:38 PM PDT 24
Finished Jul 25 06:45:32 PM PDT 24
Peak memory 660284 kb
Host smart-7249e568-7eeb-428d-9078-49217072c622
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3604315487 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_128.3604315487 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_shake_256.1169589910
Short name T421
Test name
Test status
Simulation time 361888199001 ps
CPU time 4469.26 seconds
Started Jul 25 05:13:38 PM PDT 24
Finished Jul 25 06:28:08 PM PDT 24
Peak memory 576976 kb
Host smart-7e67e10d-74cd-45d3-a1f1-2f3a974c0ce1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1169589910 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_256.1169589910 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/17.kmac_alert_test.476996170
Short name T1037
Test name
Test status
Simulation time 17501400 ps
CPU time 0.84 seconds
Started Jul 25 05:13:50 PM PDT 24
Finished Jul 25 05:13:52 PM PDT 24
Peak memory 218212 kb
Host smart-8ea92699-d280-40e6-bc27-12946040590f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476996170 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.476996170 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/17.kmac_alert_test/latest

Test location /workspace/coverage/default/17.kmac_app.1892435044
Short name T145
Test name
Test status
Simulation time 13029091053 ps
CPU time 303.06 seconds
Started Jul 25 05:13:51 PM PDT 24
Finished Jul 25 05:18:55 PM PDT 24
Peak memory 249428 kb
Host smart-92985447-664d-443d-b715-2002d8aa4515
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892435044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.1892435044 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/17.kmac_app/latest

Test location /workspace/coverage/default/17.kmac_burst_write.2644186813
Short name T417
Test name
Test status
Simulation time 32019380221 ps
CPU time 1201.66 seconds
Started Jul 25 05:13:39 PM PDT 24
Finished Jul 25 05:33:41 PM PDT 24
Peak memory 238428 kb
Host smart-764982c3-3ba6-497e-885d-2da84c67f8a8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644186813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.264418681
3 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_burst_write/latest

Test location /workspace/coverage/default/17.kmac_edn_timeout_error.376664793
Short name T3
Test name
Test status
Simulation time 67248208 ps
CPU time 5.16 seconds
Started Jul 25 05:13:50 PM PDT 24
Finished Jul 25 05:13:55 PM PDT 24
Peak memory 225748 kb
Host smart-87a40216-a64c-44fa-9b97-3fcc31bfc6a5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=376664793 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.376664793 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_mode_error.490688518
Short name T327
Test name
Test status
Simulation time 107520872 ps
CPU time 3.89 seconds
Started Jul 25 05:13:52 PM PDT 24
Finished Jul 25 05:13:56 PM PDT 24
Peak memory 226484 kb
Host smart-90eeb95f-8be5-4ae5-bd51-1d60968d523e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=490688518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.490688518 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_refresh.1932839282
Short name T993
Test name
Test status
Simulation time 2242554111 ps
CPU time 95.46 seconds
Started Jul 25 05:13:51 PM PDT 24
Finished Jul 25 05:15:27 PM PDT 24
Peak memory 232872 kb
Host smart-57276dff-e66e-4577-bdf1-b26e155defcd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932839282 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.1
932839282 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/17.kmac_error.580311251
Short name T549
Test name
Test status
Simulation time 11316399133 ps
CPU time 97.41 seconds
Started Jul 25 05:13:50 PM PDT 24
Finished Jul 25 05:15:27 PM PDT 24
Peak memory 243148 kb
Host smart-0c883927-9d9d-4956-96e1-068b67fc5b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580311251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.580311251 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_error/latest

Test location /workspace/coverage/default/17.kmac_key_error.1872577230
Short name T760
Test name
Test status
Simulation time 806598461 ps
CPU time 4.51 seconds
Started Jul 25 05:13:51 PM PDT 24
Finished Jul 25 05:13:56 PM PDT 24
Peak memory 222988 kb
Host smart-48d45e04-c2e4-45d4-bdb7-cebf1a085fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872577230 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.1872577230 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_key_error/latest

Test location /workspace/coverage/default/17.kmac_long_msg_and_output.2499466218
Short name T240
Test name
Test status
Simulation time 2433666208 ps
CPU time 33.23 seconds
Started Jul 25 05:13:40 PM PDT 24
Finished Jul 25 05:14:14 PM PDT 24
Peak memory 221576 kb
Host smart-0452008f-c962-488d-b48f-d3758fa9ada9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499466218 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_a
nd_output.2499466218 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/17.kmac_sideload.2224175928
Short name T202
Test name
Test status
Simulation time 16008394842 ps
CPU time 255.88 seconds
Started Jul 25 05:13:43 PM PDT 24
Finished Jul 25 05:17:59 PM PDT 24
Peak memory 243228 kb
Host smart-113e24cc-6507-4bf4-bb3e-2761223f8ee8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224175928 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.2224175928 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_sideload/latest

Test location /workspace/coverage/default/17.kmac_smoke.4001609101
Short name T534
Test name
Test status
Simulation time 2283673396 ps
CPU time 52.28 seconds
Started Jul 25 05:13:40 PM PDT 24
Finished Jul 25 05:14:32 PM PDT 24
Peak memory 226640 kb
Host smart-39fe5633-ecae-4217-b963-0ee2bb2b854a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001609101 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.4001609101 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_smoke/latest

Test location /workspace/coverage/default/17.kmac_stress_all.1171381536
Short name T995
Test name
Test status
Simulation time 40223512133 ps
CPU time 521.4 seconds
Started Jul 25 05:13:53 PM PDT 24
Finished Jul 25 05:22:34 PM PDT 24
Peak memory 275896 kb
Host smart-cc0aacd7-d4b2-47d5-8a67-b1ce6e7bceac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1171381536 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.1171381536 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_stress_all/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_kmac.3377647636
Short name T830
Test name
Test status
Simulation time 438456931 ps
CPU time 5.37 seconds
Started Jul 25 05:13:52 PM PDT 24
Finished Jul 25 05:13:57 PM PDT 24
Peak memory 218488 kb
Host smart-cfe05091-5645-495d-a605-071e3fedd38d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377647636 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.kmac_test_vectors_kmac.3377647636 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_kmac_xof.690109235
Short name T886
Test name
Test status
Simulation time 193547944 ps
CPU time 6.22 seconds
Started Jul 25 05:13:50 PM PDT 24
Finished Jul 25 05:13:57 PM PDT 24
Peak memory 218544 kb
Host smart-183e3247-3e3f-49f9-8be9-35a5e098599a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690109235 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.kmac_test_vectors_kmac_xof.690109235 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_224.3633654949
Short name T541
Test name
Test status
Simulation time 258904147041 ps
CPU time 2191.62 seconds
Started Jul 25 05:13:42 PM PDT 24
Finished Jul 25 05:50:14 PM PDT 24
Peak memory 391796 kb
Host smart-6dd4ca77-4523-4253-adfd-9b4a5417b4fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3633654949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_224.3633654949 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_256.3394444791
Short name T1036
Test name
Test status
Simulation time 241120893935 ps
CPU time 1983.27 seconds
Started Jul 25 05:13:38 PM PDT 24
Finished Jul 25 05:46:41 PM PDT 24
Peak memory 377884 kb
Host smart-ff5cf489-b66a-4bbd-bfaf-a671c93bf75c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3394444791 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_256.3394444791 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_384.858353801
Short name T986
Test name
Test status
Simulation time 32383284631 ps
CPU time 1549.19 seconds
Started Jul 25 05:13:43 PM PDT 24
Finished Jul 25 05:39:33 PM PDT 24
Peak memory 342488 kb
Host smart-33971dfb-def5-465e-8019-7ace98413e2d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=858353801 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_384.858353801 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_512.2131792658
Short name T450
Test name
Test status
Simulation time 141912305574 ps
CPU time 1254.6 seconds
Started Jul 25 05:13:40 PM PDT 24
Finished Jul 25 05:34:35 PM PDT 24
Peak memory 297620 kb
Host smart-bce7c59c-d18a-4931-9829-cf6da2163f46
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2131792658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_512.2131792658 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_shake_128.730286755
Short name T592
Test name
Test status
Simulation time 720411326922 ps
CPU time 5670.59 seconds
Started Jul 25 05:13:38 PM PDT 24
Finished Jul 25 06:48:10 PM PDT 24
Peak memory 658720 kb
Host smart-035456c1-4051-4ed3-97c4-57dd644dba6c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=730286755 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_128.730286755 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_shake_256.2894908834
Short name T254
Test name
Test status
Simulation time 106883391387 ps
CPU time 4280.72 seconds
Started Jul 25 05:13:53 PM PDT 24
Finished Jul 25 06:25:15 PM PDT 24
Peak memory 568028 kb
Host smart-0a135ab7-6dee-495b-8fb2-c59be2425a18
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2894908834 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_256.2894908834 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/18.kmac_alert_test.3253581585
Short name T695
Test name
Test status
Simulation time 17122640 ps
CPU time 0.79 seconds
Started Jul 25 05:13:53 PM PDT 24
Finished Jul 25 05:13:54 PM PDT 24
Peak memory 218224 kb
Host smart-b46a204a-86e8-452a-b371-efaf7afc1d50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253581585 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.3253581585 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_alert_test/latest

Test location /workspace/coverage/default/18.kmac_app.830355957
Short name T951
Test name
Test status
Simulation time 18657281672 ps
CPU time 307.31 seconds
Started Jul 25 05:13:50 PM PDT 24
Finished Jul 25 05:18:58 PM PDT 24
Peak memory 248380 kb
Host smart-11059d88-9cdc-43d4-9a9d-77546d53632f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830355957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.830355957 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/18.kmac_app/latest

Test location /workspace/coverage/default/18.kmac_burst_write.4220402393
Short name T365
Test name
Test status
Simulation time 79922150429 ps
CPU time 1003.15 seconds
Started Jul 25 05:13:50 PM PDT 24
Finished Jul 25 05:30:33 PM PDT 24
Peak memory 237976 kb
Host smart-6195a0be-0f46-4b1b-b989-6dae21359d64
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220402393 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.422040239
3 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_burst_write/latest

Test location /workspace/coverage/default/18.kmac_edn_timeout_error.219399128
Short name T956
Test name
Test status
Simulation time 17862077 ps
CPU time 0.83 seconds
Started Jul 25 05:13:59 PM PDT 24
Finished Jul 25 05:14:00 PM PDT 24
Peak memory 218288 kb
Host smart-87be8ed1-31f6-436c-b5fd-c3f0f58ee541
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=219399128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.219399128 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_mode_error.2197969738
Short name T266
Test name
Test status
Simulation time 1089610359 ps
CPU time 40.55 seconds
Started Jul 25 05:13:53 PM PDT 24
Finished Jul 25 05:14:34 PM PDT 24
Peak memory 226472 kb
Host smart-18f6cec1-103e-4162-b706-2a410d43922f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2197969738 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.2197969738 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_refresh.4147398431
Short name T436
Test name
Test status
Simulation time 17849891151 ps
CPU time 310.6 seconds
Started Jul 25 05:13:50 PM PDT 24
Finished Jul 25 05:19:01 PM PDT 24
Peak memory 249004 kb
Host smart-27248a47-e743-416c-ad2a-66ad5d9ecf74
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147398431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.4
147398431 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/18.kmac_error.587414521
Short name T972
Test name
Test status
Simulation time 58129640841 ps
CPU time 301.65 seconds
Started Jul 25 05:13:50 PM PDT 24
Finished Jul 25 05:18:52 PM PDT 24
Peak memory 251240 kb
Host smart-0bd30abe-2138-4999-805b-38f2c005ac1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587414521 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.587414521 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_error/latest

Test location /workspace/coverage/default/18.kmac_key_error.3453654921
Short name T1011
Test name
Test status
Simulation time 5748101718 ps
CPU time 10.48 seconds
Started Jul 25 05:13:53 PM PDT 24
Finished Jul 25 05:14:04 PM PDT 24
Peak memory 225196 kb
Host smart-4862cac6-fd33-4e56-936e-eab4063fda5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453654921 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.3453654921 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_key_error/latest

Test location /workspace/coverage/default/18.kmac_lc_escalation.1225967526
Short name T117
Test name
Test status
Simulation time 65247762 ps
CPU time 1.49 seconds
Started Jul 25 05:14:01 PM PDT 24
Finished Jul 25 05:14:03 PM PDT 24
Peak memory 226604 kb
Host smart-03109011-b71e-49b4-b327-6310a8963c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225967526 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.1225967526 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/18.kmac_lc_escalation/latest

Test location /workspace/coverage/default/18.kmac_long_msg_and_output.1606206805
Short name T342
Test name
Test status
Simulation time 82697414652 ps
CPU time 1246.23 seconds
Started Jul 25 05:13:52 PM PDT 24
Finished Jul 25 05:34:39 PM PDT 24
Peak memory 318600 kb
Host smart-5cdda3e1-0643-4cce-85d5-dda2ae7c89cc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606206805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_a
nd_output.1606206805 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/18.kmac_sideload.3215184911
Short name T377
Test name
Test status
Simulation time 16460536773 ps
CPU time 437.44 seconds
Started Jul 25 05:13:53 PM PDT 24
Finished Jul 25 05:21:10 PM PDT 24
Peak memory 253532 kb
Host smart-15cd390a-5633-45ce-8725-06f622161a74
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215184911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.3215184911 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_sideload/latest

Test location /workspace/coverage/default/18.kmac_smoke.203953083
Short name T40
Test name
Test status
Simulation time 2041723386 ps
CPU time 20.17 seconds
Started Jul 25 05:13:54 PM PDT 24
Finished Jul 25 05:14:14 PM PDT 24
Peak memory 226388 kb
Host smart-0838ab4b-177f-4c35-a263-0e0e8c2ea710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203953083 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.203953083 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_smoke/latest

Test location /workspace/coverage/default/18.kmac_stress_all.2572458844
Short name T319
Test name
Test status
Simulation time 28990315729 ps
CPU time 388.43 seconds
Started Jul 25 05:13:50 PM PDT 24
Finished Jul 25 05:20:19 PM PDT 24
Peak memory 276080 kb
Host smart-4996f871-38df-4be5-ac0e-acd30bfb95eb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2572458844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.2572458844 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_stress_all/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_kmac.3862674389
Short name T997
Test name
Test status
Simulation time 206011183 ps
CPU time 6.28 seconds
Started Jul 25 05:13:51 PM PDT 24
Finished Jul 25 05:13:57 PM PDT 24
Peak memory 219480 kb
Host smart-5411b85f-f358-4ffc-b1db-59b77522330d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862674389 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.kmac_test_vectors_kmac.3862674389 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_kmac_xof.704197768
Short name T717
Test name
Test status
Simulation time 3097254013 ps
CPU time 7.59 seconds
Started Jul 25 05:13:55 PM PDT 24
Finished Jul 25 05:14:02 PM PDT 24
Peak memory 218636 kb
Host smart-75502c1d-a719-4444-b529-f87edd9fb446
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704197768 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.kmac_test_vectors_kmac_xof.704197768 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_224.3665567031
Short name T454
Test name
Test status
Simulation time 70576170268 ps
CPU time 2174.8 seconds
Started Jul 25 05:13:53 PM PDT 24
Finished Jul 25 05:50:08 PM PDT 24
Peak memory 398888 kb
Host smart-9d1c0b9a-1f55-40f9-bcab-39a00e13be53
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3665567031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_224.3665567031 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_256.560165015
Short name T733
Test name
Test status
Simulation time 534532705680 ps
CPU time 2298.9 seconds
Started Jul 25 05:13:54 PM PDT 24
Finished Jul 25 05:52:13 PM PDT 24
Peak memory 383276 kb
Host smart-d3e7235a-cd50-477d-8d77-6b6dd7259bf7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=560165015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_256.560165015 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_384.4248190660
Short name T723
Test name
Test status
Simulation time 196664018104 ps
CPU time 1590.08 seconds
Started Jul 25 05:13:49 PM PDT 24
Finished Jul 25 05:40:19 PM PDT 24
Peak memory 337636 kb
Host smart-633c1860-ae0c-4e2a-91e6-8b3d9dba6cdb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4248190660 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_384.4248190660 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_512.4249280707
Short name T423
Test name
Test status
Simulation time 11139848830 ps
CPU time 1098.09 seconds
Started Jul 25 05:13:51 PM PDT 24
Finished Jul 25 05:32:09 PM PDT 24
Peak memory 298576 kb
Host smart-49010812-0e8f-441e-9f50-e92df7258454
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4249280707 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_512.4249280707 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_shake_128.2065526455
Short name T982
Test name
Test status
Simulation time 771560139285 ps
CPU time 5359.89 seconds
Started Jul 25 05:13:49 PM PDT 24
Finished Jul 25 06:43:10 PM PDT 24
Peak memory 660716 kb
Host smart-34ff9a87-86b2-40ca-9bd8-8b1babfff57c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2065526455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_128.2065526455 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_shake_256.849669717
Short name T925
Test name
Test status
Simulation time 357911206821 ps
CPU time 4760.26 seconds
Started Jul 25 05:13:50 PM PDT 24
Finished Jul 25 06:33:12 PM PDT 24
Peak memory 572212 kb
Host smart-07fa3b23-7f3e-4e8c-9040-c46b35bba7d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=849669717 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_256.849669717 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/19.kmac_alert_test.2810255664
Short name T666
Test name
Test status
Simulation time 43528408 ps
CPU time 0.85 seconds
Started Jul 25 05:14:05 PM PDT 24
Finished Jul 25 05:14:06 PM PDT 24
Peak memory 218320 kb
Host smart-fdb1afc7-c38d-4373-ab5f-c6e2deac4dd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810255664 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.2810255664 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_alert_test/latest

Test location /workspace/coverage/default/19.kmac_app.819374437
Short name T453
Test name
Test status
Simulation time 9762679684 ps
CPU time 191.74 seconds
Started Jul 25 05:14:01 PM PDT 24
Finished Jul 25 05:17:13 PM PDT 24
Peak memory 240184 kb
Host smart-065d44cb-2afa-4b46-9e05-b3ea16272fc4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819374437 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.819374437 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/19.kmac_app/latest

Test location /workspace/coverage/default/19.kmac_burst_write.2392084814
Short name T574
Test name
Test status
Simulation time 51821447095 ps
CPU time 879.9 seconds
Started Jul 25 05:14:00 PM PDT 24
Finished Jul 25 05:28:40 PM PDT 24
Peak memory 243084 kb
Host smart-3a41f032-b806-453e-a737-e9d460bbe5ee
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392084814 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.239208481
4 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_burst_write/latest

Test location /workspace/coverage/default/19.kmac_edn_timeout_error.3130254
Short name T80
Test name
Test status
Simulation time 25546963 ps
CPU time 1.17 seconds
Started Jul 25 05:14:05 PM PDT 24
Finished Jul 25 05:14:06 PM PDT 24
Peak memory 218376 kb
Host smart-305e290f-7e00-4a58-9558-7adb4ad60940
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3130254 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.3130254 +enable_mas
king=1 +sw_key_masked=0
Directory /workspace/19.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_mode_error.3808479197
Short name T853
Test name
Test status
Simulation time 41350813 ps
CPU time 1.13 seconds
Started Jul 25 05:14:04 PM PDT 24
Finished Jul 25 05:14:05 PM PDT 24
Peak memory 222092 kb
Host smart-69a62194-4dd7-4e3d-9206-d0908f595b80
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3808479197 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.3808479197 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_refresh.6691714
Short name T586
Test name
Test status
Simulation time 44917633810 ps
CPU time 217.38 seconds
Started Jul 25 05:14:02 PM PDT 24
Finished Jul 25 05:17:39 PM PDT 24
Peak memory 243700 kb
Host smart-67e83a37-af0b-43a4-9618-17aab01e3524
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6691714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.6691
714 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/19.kmac_error.4173235829
Short name T991
Test name
Test status
Simulation time 5025067755 ps
CPU time 104.45 seconds
Started Jul 25 05:14:03 PM PDT 24
Finished Jul 25 05:15:48 PM PDT 24
Peak memory 252548 kb
Host smart-31307db5-f3be-4fdb-aaf2-e7dac208679f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173235829 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.4173235829 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_error/latest

Test location /workspace/coverage/default/19.kmac_key_error.383992532
Short name T764
Test name
Test status
Simulation time 883891513 ps
CPU time 7.51 seconds
Started Jul 25 05:14:01 PM PDT 24
Finished Jul 25 05:14:09 PM PDT 24
Peak memory 223152 kb
Host smart-e1d104af-c094-48a7-899d-5450339ed5fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383992532 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.383992532 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_key_error/latest

Test location /workspace/coverage/default/19.kmac_lc_escalation.1453684968
Short name T72
Test name
Test status
Simulation time 45898185 ps
CPU time 1.42 seconds
Started Jul 25 05:14:01 PM PDT 24
Finished Jul 25 05:14:03 PM PDT 24
Peak memory 226568 kb
Host smart-af1ee954-98be-4345-97b2-75f96b895683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453684968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.1453684968 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/19.kmac_lc_escalation/latest

Test location /workspace/coverage/default/19.kmac_long_msg_and_output.1976121808
Short name T201
Test name
Test status
Simulation time 803855143602 ps
CPU time 2757.39 seconds
Started Jul 25 05:13:49 PM PDT 24
Finished Jul 25 05:59:47 PM PDT 24
Peak memory 442992 kb
Host smart-b6f1aaf4-c9da-4bda-bc2a-b4c2e6bffd07
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976121808 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_a
nd_output.1976121808 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/19.kmac_sideload.301125966
Short name T1017
Test name
Test status
Simulation time 4406462619 ps
CPU time 148.84 seconds
Started Jul 25 05:13:52 PM PDT 24
Finished Jul 25 05:16:21 PM PDT 24
Peak memory 233596 kb
Host smart-ed503820-4407-4466-bac0-9e21044dc9f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301125966 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.301125966 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_sideload/latest

Test location /workspace/coverage/default/19.kmac_smoke.1108966046
Short name T256
Test name
Test status
Simulation time 1924914680 ps
CPU time 26.07 seconds
Started Jul 25 05:13:51 PM PDT 24
Finished Jul 25 05:14:17 PM PDT 24
Peak memory 226412 kb
Host smart-eb5f7fd2-1ce0-4c22-bab1-b4adc6dba0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108966046 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.1108966046 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_smoke/latest

Test location /workspace/coverage/default/19.kmac_stress_all.150081223
Short name T63
Test name
Test status
Simulation time 27033128733 ps
CPU time 2214.96 seconds
Started Jul 25 05:13:59 PM PDT 24
Finished Jul 25 05:50:54 PM PDT 24
Peak memory 439840 kb
Host smart-e22e849e-abbd-42a3-9daf-2cc1158804ef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=150081223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.150081223 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_stress_all/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_kmac.3219916787
Short name T326
Test name
Test status
Simulation time 110526084 ps
CPU time 5.74 seconds
Started Jul 25 05:14:06 PM PDT 24
Finished Jul 25 05:14:12 PM PDT 24
Peak memory 218644 kb
Host smart-5c6c03dd-ef0d-4502-bcd5-7decbbd0ddbd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219916787 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.kmac_test_vectors_kmac.3219916787 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_kmac_xof.4284292498
Short name T1046
Test name
Test status
Simulation time 396792692 ps
CPU time 5.49 seconds
Started Jul 25 05:14:00 PM PDT 24
Finished Jul 25 05:14:06 PM PDT 24
Peak memory 219412 kb
Host smart-d1372a2e-e93c-4c0a-8b77-cc8f723162ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284292498 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.kmac_test_vectors_kmac_xof.4284292498 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_224.1032230818
Short name T362
Test name
Test status
Simulation time 25894371303 ps
CPU time 1962.18 seconds
Started Jul 25 05:14:00 PM PDT 24
Finished Jul 25 05:46:43 PM PDT 24
Peak memory 399020 kb
Host smart-3f2263cd-9664-43b2-8d3f-015ab37a8b74
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1032230818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_224.1032230818 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_256.3683235940
Short name T909
Test name
Test status
Simulation time 243146244036 ps
CPU time 2017.6 seconds
Started Jul 25 05:14:00 PM PDT 24
Finished Jul 25 05:47:38 PM PDT 24
Peak memory 380712 kb
Host smart-f7b690cc-ee1a-4b12-a42f-0f727873429e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3683235940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_256.3683235940 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_384.252367352
Short name T467
Test name
Test status
Simulation time 139791080168 ps
CPU time 1857.52 seconds
Started Jul 25 05:14:01 PM PDT 24
Finished Jul 25 05:44:59 PM PDT 24
Peak memory 339112 kb
Host smart-eeb7f772-a35d-4eda-8ba3-47142fef00e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=252367352 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_384.252367352 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_512.3698139035
Short name T305
Test name
Test status
Simulation time 694205031103 ps
CPU time 1184.03 seconds
Started Jul 25 05:14:01 PM PDT 24
Finished Jul 25 05:33:45 PM PDT 24
Peak memory 297308 kb
Host smart-3861b703-9b81-4d7d-854a-1de55e374252
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3698139035 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_512.3698139035 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_shake_128.1255232151
Short name T619
Test name
Test status
Simulation time 84039690354 ps
CPU time 4850.97 seconds
Started Jul 25 05:14:01 PM PDT 24
Finished Jul 25 06:34:53 PM PDT 24
Peak memory 648744 kb
Host smart-7e7dff43-d12e-4fc6-996c-2f4ea97a8abc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1255232151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_128.1255232151 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_shake_256.3499073448
Short name T969
Test name
Test status
Simulation time 81128049633 ps
CPU time 4396.31 seconds
Started Jul 25 05:14:00 PM PDT 24
Finished Jul 25 06:27:17 PM PDT 24
Peak memory 576224 kb
Host smart-02e5b5d5-17cf-4f99-ab39-452d48f4f210
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3499073448 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_256.3499073448 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/2.kmac_alert_test.2037787759
Short name T284
Test name
Test status
Simulation time 14522652 ps
CPU time 0.82 seconds
Started Jul 25 05:12:14 PM PDT 24
Finished Jul 25 05:12:15 PM PDT 24
Peak memory 218304 kb
Host smart-0917ebf9-0292-47f1-9d5e-dd7d9e3857fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037787759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.2037787759 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_alert_test/latest

Test location /workspace/coverage/default/2.kmac_app.3781305829
Short name T919
Test name
Test status
Simulation time 10830227626 ps
CPU time 72.03 seconds
Started Jul 25 05:11:58 PM PDT 24
Finished Jul 25 05:13:10 PM PDT 24
Peak memory 229156 kb
Host smart-6632ff4f-7112-4362-9e0b-10437f3ce92e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781305829 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.3781305829 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/2.kmac_app/latest

Test location /workspace/coverage/default/2.kmac_app_with_partial_data.1077007642
Short name T547
Test name
Test status
Simulation time 4901895583 ps
CPU time 136.68 seconds
Started Jul 25 05:11:56 PM PDT 24
Finished Jul 25 05:14:12 PM PDT 24
Peak memory 236800 kb
Host smart-3829c217-f2e3-4313-b2a2-3b9686a96948
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077007642 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_par
tial_data.1077007642 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/2.kmac_burst_write.3437028163
Short name T605
Test name
Test status
Simulation time 79312478569 ps
CPU time 1205.15 seconds
Started Jul 25 05:11:57 PM PDT 24
Finished Jul 25 05:32:02 PM PDT 24
Peak memory 243012 kb
Host smart-b705eb3d-346c-4c27-bc32-f96f335ad3c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437028163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.3437028163
+enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_burst_write/latest

Test location /workspace/coverage/default/2.kmac_edn_timeout_error.2022384984
Short name T979
Test name
Test status
Simulation time 181425204 ps
CPU time 1.23 seconds
Started Jul 25 05:12:13 PM PDT 24
Finished Jul 25 05:12:15 PM PDT 24
Peak memory 218296 kb
Host smart-bcdb7ecf-64b3-43ba-a891-b671865e8fa4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2022384984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.2022384984 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_mode_error.2035865615
Short name T563
Test name
Test status
Simulation time 816691919 ps
CPU time 22.32 seconds
Started Jul 25 05:12:17 PM PDT 24
Finished Jul 25 05:12:40 PM PDT 24
Peak memory 226456 kb
Host smart-ec3301ee-c390-44a2-ada0-105669df9eeb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2035865615 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.2035865615 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_ready_error.176197798
Short name T758
Test name
Test status
Simulation time 6056263501 ps
CPU time 31.92 seconds
Started Jul 25 05:12:11 PM PDT 24
Finished Jul 25 05:12:44 PM PDT 24
Peak memory 218576 kb
Host smart-a92c4a5c-30c7-4df0-b6d2-57b11db7792b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176197798 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.176197798 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_refresh.3468403429
Short name T677
Test name
Test status
Simulation time 14229872277 ps
CPU time 373.66 seconds
Started Jul 25 05:11:59 PM PDT 24
Finished Jul 25 05:18:13 PM PDT 24
Peak memory 251944 kb
Host smart-fe34fce9-0381-48a6-80cb-7b1c85b7a163
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468403429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.34
68403429 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/2.kmac_error.3870803271
Short name T941
Test name
Test status
Simulation time 35123492979 ps
CPU time 290.3 seconds
Started Jul 25 05:12:13 PM PDT 24
Finished Jul 25 05:17:04 PM PDT 24
Peak memory 257892 kb
Host smart-c27e232a-2897-4024-8517-e303cb60ca9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870803271 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.3870803271 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_error/latest

Test location /workspace/coverage/default/2.kmac_key_error.4273782127
Short name T649
Test name
Test status
Simulation time 745455092 ps
CPU time 5.79 seconds
Started Jul 25 05:12:17 PM PDT 24
Finished Jul 25 05:12:23 PM PDT 24
Peak memory 223160 kb
Host smart-c326f961-fe4f-4d63-80e6-bf0b390b02d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273782127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.4273782127 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_key_error/latest

Test location /workspace/coverage/default/2.kmac_lc_escalation.3026627833
Short name T70
Test name
Test status
Simulation time 62811054 ps
CPU time 1.31 seconds
Started Jul 25 05:12:13 PM PDT 24
Finished Jul 25 05:12:14 PM PDT 24
Peak memory 226668 kb
Host smart-16057717-b83d-404a-bc2d-a483a1faccbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026627833 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.3026627833 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/2.kmac_lc_escalation/latest

Test location /workspace/coverage/default/2.kmac_long_msg_and_output.179071213
Short name T719
Test name
Test status
Simulation time 40965602908 ps
CPU time 2177.3 seconds
Started Jul 25 05:11:57 PM PDT 24
Finished Jul 25 05:48:14 PM PDT 24
Peak memory 403932 kb
Host smart-dfe23686-09b9-415d-bd13-5e4f348af427
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179071213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_and
_output.179071213 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/2.kmac_mubi.558244522
Short name T367
Test name
Test status
Simulation time 7052498123 ps
CPU time 224.28 seconds
Started Jul 25 05:12:27 PM PDT 24
Finished Jul 25 05:16:12 PM PDT 24
Peak memory 244040 kb
Host smart-7b29a2ff-1063-4f58-b98d-dcc75ac976f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558244522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.558244522 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_mubi/latest

Test location /workspace/coverage/default/2.kmac_sideload.2533314506
Short name T739
Test name
Test status
Simulation time 36554837556 ps
CPU time 427.97 seconds
Started Jul 25 05:11:57 PM PDT 24
Finished Jul 25 05:19:06 PM PDT 24
Peak memory 251836 kb
Host smart-c97fa11c-46db-4f0f-a3be-e28db7027426
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533314506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.2533314506 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_sideload/latest

Test location /workspace/coverage/default/2.kmac_smoke.2588235621
Short name T787
Test name
Test status
Simulation time 3641432400 ps
CPU time 70.32 seconds
Started Jul 25 05:11:57 PM PDT 24
Finished Jul 25 05:13:08 PM PDT 24
Peak memory 226576 kb
Host smart-d8301d8f-1cd7-41fe-b2e5-1b712648e049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588235621 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.2588235621 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_smoke/latest

Test location /workspace/coverage/default/2.kmac_stress_all.2368357664
Short name T1010
Test name
Test status
Simulation time 27603192756 ps
CPU time 777.13 seconds
Started Jul 25 05:12:23 PM PDT 24
Finished Jul 25 05:25:20 PM PDT 24
Peak memory 308844 kb
Host smart-413375ba-a618-44a8-a528-3185af3c136c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2368357664 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.2368357664 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_stress_all/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac.1323971959
Short name T449
Test name
Test status
Simulation time 290702209 ps
CPU time 5.33 seconds
Started Jul 25 05:12:05 PM PDT 24
Finished Jul 25 05:12:10 PM PDT 24
Peak memory 218520 kb
Host smart-d64c89d0-1fb3-406c-a011-0a1001cf0deb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323971959 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.kmac_test_vectors_kmac.1323971959 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac_xof.3326495539
Short name T584
Test name
Test status
Simulation time 560199214 ps
CPU time 6.8 seconds
Started Jul 25 05:11:55 PM PDT 24
Finished Jul 25 05:12:02 PM PDT 24
Peak memory 218692 kb
Host smart-72236eee-d731-49fe-a62f-443d324bd101
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326495539 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.kmac_test_vectors_kmac_xof.3326495539 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_224.1996136162
Short name T880
Test name
Test status
Simulation time 382783369705 ps
CPU time 2510.7 seconds
Started Jul 25 05:12:15 PM PDT 24
Finished Jul 25 05:54:06 PM PDT 24
Peak memory 390444 kb
Host smart-7a7acf72-b6da-4a53-b712-2580976e9b96
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1996136162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.1996136162 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_256.198062444
Short name T855
Test name
Test status
Simulation time 240633505068 ps
CPU time 2116.67 seconds
Started Jul 25 05:11:57 PM PDT 24
Finished Jul 25 05:47:14 PM PDT 24
Peak memory 377388 kb
Host smart-02c44c9c-b8ee-4fc4-b391-21fe29e1f332
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=198062444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.198062444 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_384.1988250583
Short name T735
Test name
Test status
Simulation time 193113789022 ps
CPU time 1722.25 seconds
Started Jul 25 05:12:15 PM PDT 24
Finished Jul 25 05:40:57 PM PDT 24
Peak memory 345052 kb
Host smart-71d4b188-d8d2-4fdf-841d-b99e0a193c93
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1988250583 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.1988250583 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_512.1488506098
Short name T811
Test name
Test status
Simulation time 141019992405 ps
CPU time 1310.92 seconds
Started Jul 25 05:12:00 PM PDT 24
Finished Jul 25 05:33:52 PM PDT 24
Peak memory 303020 kb
Host smart-c364e347-cfc9-474c-b19b-2ac73c90f505
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1488506098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.1488506098 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_128.1233332836
Short name T394
Test name
Test status
Simulation time 382438408248 ps
CPU time 5507.3 seconds
Started Jul 25 05:11:59 PM PDT 24
Finished Jul 25 06:43:47 PM PDT 24
Peak memory 672064 kb
Host smart-5003eeae-3865-47dd-9245-54d953bb934b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1233332836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.1233332836 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_256.1928226271
Short name T950
Test name
Test status
Simulation time 154152682693 ps
CPU time 4245.47 seconds
Started Jul 25 05:11:58 PM PDT 24
Finished Jul 25 06:22:44 PM PDT 24
Peak memory 577468 kb
Host smart-3db7aefa-d8da-40ae-ba6c-2b74d63a0aaf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1928226271 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.1928226271 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/20.kmac_alert_test.4164814402
Short name T642
Test name
Test status
Simulation time 39994616 ps
CPU time 0.87 seconds
Started Jul 25 05:14:09 PM PDT 24
Finished Jul 25 05:14:10 PM PDT 24
Peak memory 218256 kb
Host smart-3da5dbd8-6224-4485-99ec-1ae67737e945
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164814402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.4164814402 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_alert_test/latest

Test location /workspace/coverage/default/20.kmac_app.2206521564
Short name T270
Test name
Test status
Simulation time 5776529229 ps
CPU time 383.65 seconds
Started Jul 25 05:14:10 PM PDT 24
Finished Jul 25 05:20:34 PM PDT 24
Peak memory 254456 kb
Host smart-952c7b75-9438-4c7c-a594-ca131f49723e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206521564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.2206521564 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/20.kmac_app/latest

Test location /workspace/coverage/default/20.kmac_burst_write.264958410
Short name T406
Test name
Test status
Simulation time 31093080538 ps
CPU time 1156.06 seconds
Started Jul 25 05:14:00 PM PDT 24
Finished Jul 25 05:33:16 PM PDT 24
Peak memory 243032 kb
Host smart-13b381cb-43dc-45f0-b63e-1812e27efa50
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264958410 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.264958410
+enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_burst_write/latest

Test location /workspace/coverage/default/20.kmac_entropy_refresh.3253793763
Short name T702
Test name
Test status
Simulation time 2569252010 ps
CPU time 65.63 seconds
Started Jul 25 05:14:09 PM PDT 24
Finished Jul 25 05:15:15 PM PDT 24
Peak memory 228672 kb
Host smart-133ee756-2258-4358-bb1a-b9078d393b40
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253793763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.3
253793763 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/20.kmac_key_error.1702417592
Short name T634
Test name
Test status
Simulation time 1001299792 ps
CPU time 2.97 seconds
Started Jul 25 05:14:09 PM PDT 24
Finished Jul 25 05:14:12 PM PDT 24
Peak memory 222492 kb
Host smart-e22577b8-1a95-4a23-a29e-086b5d77503f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702417592 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.1702417592 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_key_error/latest

Test location /workspace/coverage/default/20.kmac_lc_escalation.1800439653
Short name T660
Test name
Test status
Simulation time 73408194 ps
CPU time 1.6 seconds
Started Jul 25 05:14:11 PM PDT 24
Finished Jul 25 05:14:13 PM PDT 24
Peak memory 226640 kb
Host smart-b9df4d85-30d6-479e-96a6-889601641ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800439653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.1800439653 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/20.kmac_lc_escalation/latest

Test location /workspace/coverage/default/20.kmac_long_msg_and_output.4102098570
Short name T471
Test name
Test status
Simulation time 11269813797 ps
CPU time 454.71 seconds
Started Jul 25 05:14:00 PM PDT 24
Finished Jul 25 05:21:35 PM PDT 24
Peak memory 262464 kb
Host smart-1916473f-a700-4d75-b346-3fa7700641aa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102098570 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_a
nd_output.4102098570 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/20.kmac_sideload.2045882982
Short name T225
Test name
Test status
Simulation time 1207348441 ps
CPU time 85.61 seconds
Started Jul 25 05:14:05 PM PDT 24
Finished Jul 25 05:15:31 PM PDT 24
Peak memory 230892 kb
Host smart-2f150c5d-375a-4425-9b81-65be924e25bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045882982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.2045882982 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_sideload/latest

Test location /workspace/coverage/default/20.kmac_smoke.2739119091
Short name T426
Test name
Test status
Simulation time 4698547593 ps
CPU time 60.94 seconds
Started Jul 25 05:14:02 PM PDT 24
Finished Jul 25 05:15:03 PM PDT 24
Peak memory 219324 kb
Host smart-8871d6f5-9616-4dd2-8814-12624b6d5041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739119091 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.2739119091 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_smoke/latest

Test location /workspace/coverage/default/20.kmac_stress_all.3089792776
Short name T151
Test name
Test status
Simulation time 25068159107 ps
CPU time 483.85 seconds
Started Jul 25 05:14:09 PM PDT 24
Finished Jul 25 05:22:13 PM PDT 24
Peak memory 265796 kb
Host smart-06e0f538-3ca7-4817-8e59-7806db08af30
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3089792776 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.3089792776 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_stress_all/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_kmac.2717081392
Short name T488
Test name
Test status
Simulation time 565102655 ps
CPU time 6.88 seconds
Started Jul 25 05:14:02 PM PDT 24
Finished Jul 25 05:14:09 PM PDT 24
Peak memory 218536 kb
Host smart-a8189ffe-464b-4d29-9a62-12ef1d00e0d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717081392 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.kmac_test_vectors_kmac.2717081392 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_kmac_xof.2602791506
Short name T1026
Test name
Test status
Simulation time 181161439 ps
CPU time 6.81 seconds
Started Jul 25 05:13:59 PM PDT 24
Finished Jul 25 05:14:06 PM PDT 24
Peak memory 219524 kb
Host smart-900e2345-ed7b-4437-87d6-751f1cd83ecf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602791506 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.kmac_test_vectors_kmac_xof.2602791506 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_224.3958763945
Short name T656
Test name
Test status
Simulation time 73689623807 ps
CPU time 2173.16 seconds
Started Jul 25 05:14:01 PM PDT 24
Finished Jul 25 05:50:14 PM PDT 24
Peak memory 401928 kb
Host smart-bdf93e8e-a1e6-4343-b16f-d332dfa611cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3958763945 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_224.3958763945 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_256.2265778758
Short name T750
Test name
Test status
Simulation time 64613586108 ps
CPU time 1997.86 seconds
Started Jul 25 05:14:05 PM PDT 24
Finished Jul 25 05:47:23 PM PDT 24
Peak memory 379144 kb
Host smart-1a51b9d6-a85a-4e4e-803a-f80f1b3cdeea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2265778758 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_256.2265778758 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_384.841308300
Short name T904
Test name
Test status
Simulation time 62250311774 ps
CPU time 1616.77 seconds
Started Jul 25 05:14:00 PM PDT 24
Finished Jul 25 05:40:57 PM PDT 24
Peak memory 340448 kb
Host smart-313ab97f-af76-4544-a691-38ad5fb5390a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=841308300 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_384.841308300 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_512.3216472111
Short name T39
Test name
Test status
Simulation time 45218129133 ps
CPU time 1132.39 seconds
Started Jul 25 05:14:07 PM PDT 24
Finished Jul 25 05:33:00 PM PDT 24
Peak memory 303596 kb
Host smart-89b86d7a-92a9-4191-b0ce-ed9f33818232
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3216472111 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_512.3216472111 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_shake_128.2338760973
Short name T229
Test name
Test status
Simulation time 738616966852 ps
CPU time 5302.21 seconds
Started Jul 25 05:14:01 PM PDT 24
Finished Jul 25 06:42:24 PM PDT 24
Peak memory 661716 kb
Host smart-c9f40a4c-9225-4365-a498-d3b7575c9d1f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2338760973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_128.2338760973 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_shake_256.2272632387
Short name T287
Test name
Test status
Simulation time 109128543010 ps
CPU time 4469.47 seconds
Started Jul 25 05:14:01 PM PDT 24
Finished Jul 25 06:28:31 PM PDT 24
Peak memory 576832 kb
Host smart-aace0acd-6c73-40d9-92cc-6a153398fb9b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2272632387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_256.2272632387 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/21.kmac_alert_test.2341092467
Short name T373
Test name
Test status
Simulation time 16054146 ps
CPU time 0.88 seconds
Started Jul 25 05:14:25 PM PDT 24
Finished Jul 25 05:14:26 PM PDT 24
Peak memory 218280 kb
Host smart-5d3053e3-2ca8-4f58-9a1c-8399a6838a09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341092467 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.2341092467 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_alert_test/latest

Test location /workspace/coverage/default/21.kmac_app.3336813334
Short name T933
Test name
Test status
Simulation time 26408384142 ps
CPU time 349.55 seconds
Started Jul 25 05:14:12 PM PDT 24
Finished Jul 25 05:20:02 PM PDT 24
Peak memory 249768 kb
Host smart-262f2dc7-9ba3-4f1e-82e0-2bcdaf56ccb6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336813334 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.3336813334 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/21.kmac_app/latest

Test location /workspace/coverage/default/21.kmac_burst_write.2194985538
Short name T381
Test name
Test status
Simulation time 13742670547 ps
CPU time 610.17 seconds
Started Jul 25 05:14:10 PM PDT 24
Finished Jul 25 05:24:20 PM PDT 24
Peak memory 243004 kb
Host smart-36a380fa-81bd-4a48-963e-ade1f57d65ea
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194985538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.219498553
8 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_burst_write/latest

Test location /workspace/coverage/default/21.kmac_entropy_refresh.3114591005
Short name T321
Test name
Test status
Simulation time 8669986454 ps
CPU time 308.04 seconds
Started Jul 25 05:14:14 PM PDT 24
Finished Jul 25 05:19:22 PM PDT 24
Peak memory 248052 kb
Host smart-cd071547-0564-4824-9cde-1355af73ab9d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114591005 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.3
114591005 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/21.kmac_error.4244722033
Short name T331
Test name
Test status
Simulation time 11389886245 ps
CPU time 227.48 seconds
Started Jul 25 05:14:11 PM PDT 24
Finished Jul 25 05:17:58 PM PDT 24
Peak memory 259428 kb
Host smart-65673b25-ce82-49a3-96c7-1da4c784e92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244722033 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.4244722033 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_error/latest

Test location /workspace/coverage/default/21.kmac_key_error.2546315348
Short name T784
Test name
Test status
Simulation time 1123027568 ps
CPU time 8.92 seconds
Started Jul 25 05:14:10 PM PDT 24
Finished Jul 25 05:14:19 PM PDT 24
Peak memory 223876 kb
Host smart-17058ce7-0a26-4f1b-bbf2-0eb0d6a7a6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546315348 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.2546315348 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_key_error/latest

Test location /workspace/coverage/default/21.kmac_lc_escalation.114947449
Short name T46
Test name
Test status
Simulation time 317728591 ps
CPU time 28.72 seconds
Started Jul 25 05:14:23 PM PDT 24
Finished Jul 25 05:14:51 PM PDT 24
Peak memory 234928 kb
Host smart-55771838-c316-4491-a4e4-696c099f6459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114947449 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.114947449 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/21.kmac_lc_escalation/latest

Test location /workspace/coverage/default/21.kmac_long_msg_and_output.3341773071
Short name T295
Test name
Test status
Simulation time 845941637251 ps
CPU time 2455.44 seconds
Started Jul 25 05:14:09 PM PDT 24
Finished Jul 25 05:55:05 PM PDT 24
Peak memory 396288 kb
Host smart-66b9542f-2c7f-48fa-beb5-1b9a1c1e4aef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341773071 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_a
nd_output.3341773071 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/21.kmac_sideload.4289887342
Short name T512
Test name
Test status
Simulation time 25022034577 ps
CPU time 216.48 seconds
Started Jul 25 05:14:11 PM PDT 24
Finished Jul 25 05:17:47 PM PDT 24
Peak memory 240668 kb
Host smart-c6b5f593-67e0-44aa-a3af-48b2e6b9a987
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289887342 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.4289887342 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_sideload/latest

Test location /workspace/coverage/default/21.kmac_smoke.3535828611
Short name T668
Test name
Test status
Simulation time 3800846736 ps
CPU time 87.29 seconds
Started Jul 25 05:14:11 PM PDT 24
Finished Jul 25 05:15:38 PM PDT 24
Peak memory 226556 kb
Host smart-c4ce848e-5975-4dc7-9e99-2f8f89af9670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535828611 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.3535828611 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_smoke/latest

Test location /workspace/coverage/default/21.kmac_stress_all.13202923
Short name T508
Test name
Test status
Simulation time 38095584472 ps
CPU time 381.17 seconds
Started Jul 25 05:14:25 PM PDT 24
Finished Jul 25 05:20:46 PM PDT 24
Peak memory 284068 kb
Host smart-72c5456b-818e-45f5-8d3a-ea5ffbebc741
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=13202923 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.13202923 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_stress_all/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_kmac.1527516111
Short name T856
Test name
Test status
Simulation time 231571940 ps
CPU time 6.06 seconds
Started Jul 25 05:14:09 PM PDT 24
Finished Jul 25 05:14:15 PM PDT 24
Peak memory 218592 kb
Host smart-4e99b50d-69a2-4eed-a609-bb16462bef9b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527516111 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.kmac_test_vectors_kmac.1527516111 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_kmac_xof.1109653415
Short name T817
Test name
Test status
Simulation time 548306999 ps
CPU time 6.01 seconds
Started Jul 25 05:14:11 PM PDT 24
Finished Jul 25 05:14:17 PM PDT 24
Peak memory 218640 kb
Host smart-02205395-b3a7-424f-aebe-62c3783c8b91
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109653415 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.kmac_test_vectors_kmac_xof.1109653415 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_224.1106778801
Short name T37
Test name
Test status
Simulation time 69154789746 ps
CPU time 2158.43 seconds
Started Jul 25 05:14:11 PM PDT 24
Finished Jul 25 05:50:10 PM PDT 24
Peak memory 402016 kb
Host smart-faf1f759-6080-4eea-8e57-18062e976e4d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1106778801 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_224.1106778801 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_256.346019160
Short name T823
Test name
Test status
Simulation time 62909246808 ps
CPU time 1930.43 seconds
Started Jul 25 05:14:11 PM PDT 24
Finished Jul 25 05:46:21 PM PDT 24
Peak memory 378228 kb
Host smart-54841324-8b85-4a81-8093-b01fde1454db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=346019160 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_256.346019160 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_384.2710658872
Short name T838
Test name
Test status
Simulation time 659099221829 ps
CPU time 1812.47 seconds
Started Jul 25 05:14:10 PM PDT 24
Finished Jul 25 05:44:22 PM PDT 24
Peak memory 332592 kb
Host smart-c446c1ed-fd9c-476e-99fa-d88e326ae5fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2710658872 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_384.2710658872 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_512.1139698586
Short name T791
Test name
Test status
Simulation time 619497540202 ps
CPU time 1548.43 seconds
Started Jul 25 05:14:10 PM PDT 24
Finished Jul 25 05:39:59 PM PDT 24
Peak memory 301508 kb
Host smart-08f73385-44a9-44ad-bd78-e8d379def35f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1139698586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_512.1139698586 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_shake_128.3333277475
Short name T292
Test name
Test status
Simulation time 258366213942 ps
CPU time 5900.64 seconds
Started Jul 25 05:14:09 PM PDT 24
Finished Jul 25 06:52:30 PM PDT 24
Peak memory 657900 kb
Host smart-b3096dc2-06d1-4155-8aa3-3d92f2a9df73
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3333277475 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_128.3333277475 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_shake_256.1708616332
Short name T620
Test name
Test status
Simulation time 163680319337 ps
CPU time 4690.45 seconds
Started Jul 25 05:14:11 PM PDT 24
Finished Jul 25 06:32:22 PM PDT 24
Peak memory 581192 kb
Host smart-0c68a989-f68b-4a19-bc87-d2e3721377e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1708616332 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_256.1708616332 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/22.kmac_alert_test.2991832711
Short name T217
Test name
Test status
Simulation time 23499703 ps
CPU time 0.78 seconds
Started Jul 25 05:14:22 PM PDT 24
Finished Jul 25 05:14:23 PM PDT 24
Peak memory 218232 kb
Host smart-2fc761e7-f88d-4981-88dd-c36906912fb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991832711 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.2991832711 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_alert_test/latest

Test location /workspace/coverage/default/22.kmac_app.3118156357
Short name T1053
Test name
Test status
Simulation time 260276949 ps
CPU time 6 seconds
Started Jul 25 05:14:29 PM PDT 24
Finished Jul 25 05:14:35 PM PDT 24
Peak memory 226620 kb
Host smart-ea1e0b3a-0fe3-4a30-a5ee-6cd90fb27ac5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118156357 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.3118156357 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/22.kmac_app/latest

Test location /workspace/coverage/default/22.kmac_burst_write.2888759903
Short name T399
Test name
Test status
Simulation time 67884114824 ps
CPU time 1651.3 seconds
Started Jul 25 05:14:23 PM PDT 24
Finished Jul 25 05:41:55 PM PDT 24
Peak memory 238276 kb
Host smart-f278263a-2b6c-44ed-847f-52dca066e445
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888759903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.288875990
3 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_burst_write/latest

Test location /workspace/coverage/default/22.kmac_entropy_refresh.1160562790
Short name T983
Test name
Test status
Simulation time 3218632221 ps
CPU time 144.44 seconds
Started Jul 25 05:14:29 PM PDT 24
Finished Jul 25 05:16:53 PM PDT 24
Peak memory 238852 kb
Host smart-eda19aa4-89ff-439f-bf80-e53101267589
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160562790 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.1
160562790 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/22.kmac_error.1164802358
Short name T397
Test name
Test status
Simulation time 970685743 ps
CPU time 32.57 seconds
Started Jul 25 05:14:27 PM PDT 24
Finished Jul 25 05:14:59 PM PDT 24
Peak memory 239104 kb
Host smart-bd4a2af1-7bbf-44b5-a0f1-fc597ca90bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164802358 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.1164802358 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_error/latest

Test location /workspace/coverage/default/22.kmac_key_error.3273274168
Short name T590
Test name
Test status
Simulation time 791553177 ps
CPU time 7 seconds
Started Jul 25 05:14:24 PM PDT 24
Finished Jul 25 05:14:31 PM PDT 24
Peak memory 223280 kb
Host smart-e8dd0fc5-f309-4eb0-b974-37605babf702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273274168 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.3273274168 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_key_error/latest

Test location /workspace/coverage/default/22.kmac_lc_escalation.1184759273
Short name T1024
Test name
Test status
Simulation time 97459634 ps
CPU time 1.32 seconds
Started Jul 25 05:14:28 PM PDT 24
Finished Jul 25 05:14:29 PM PDT 24
Peak memory 226672 kb
Host smart-9add3892-458c-4828-89cb-e80b01512a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184759273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.1184759273 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/22.kmac_lc_escalation/latest

Test location /workspace/coverage/default/22.kmac_long_msg_and_output.1607826865
Short name T204
Test name
Test status
Simulation time 464060818219 ps
CPU time 3121.81 seconds
Started Jul 25 05:14:24 PM PDT 24
Finished Jul 25 06:06:26 PM PDT 24
Peak memory 455292 kb
Host smart-009b658e-605a-4703-a924-916810010b18
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607826865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_a
nd_output.1607826865 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/22.kmac_sideload.2853117443
Short name T411
Test name
Test status
Simulation time 8845758227 ps
CPU time 199.66 seconds
Started Jul 25 05:14:23 PM PDT 24
Finished Jul 25 05:17:42 PM PDT 24
Peak memory 238212 kb
Host smart-ec2b6029-c708-43ed-a44b-29cbd6afbf99
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853117443 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.2853117443 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_sideload/latest

Test location /workspace/coverage/default/22.kmac_smoke.2297936713
Short name T242
Test name
Test status
Simulation time 4302801405 ps
CPU time 28.22 seconds
Started Jul 25 05:14:24 PM PDT 24
Finished Jul 25 05:14:53 PM PDT 24
Peak memory 226156 kb
Host smart-856d1764-2fda-46bb-8f54-0c04e0c96ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297936713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.2297936713 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_smoke/latest

Test location /workspace/coverage/default/22.kmac_stress_all.3297900685
Short name T740
Test name
Test status
Simulation time 28212834685 ps
CPU time 489.24 seconds
Started Jul 25 05:14:27 PM PDT 24
Finished Jul 25 05:22:36 PM PDT 24
Peak memory 267004 kb
Host smart-b5409459-1c58-4a3f-9ef1-400d462b764f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3297900685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.3297900685 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_stress_all/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_kmac.1492797045
Short name T826
Test name
Test status
Simulation time 258064709 ps
CPU time 6.4 seconds
Started Jul 25 05:14:27 PM PDT 24
Finished Jul 25 05:14:33 PM PDT 24
Peak memory 218668 kb
Host smart-4d0f82c4-c475-4f86-b131-122211a33dff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492797045 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.kmac_test_vectors_kmac.1492797045 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_kmac_xof.1241983825
Short name T230
Test name
Test status
Simulation time 309560738 ps
CPU time 6.27 seconds
Started Jul 25 05:14:24 PM PDT 24
Finished Jul 25 05:14:30 PM PDT 24
Peak memory 218592 kb
Host smart-fd9a7719-5c89-419a-b453-258ad9ef4c9b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241983825 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.kmac_test_vectors_kmac_xof.1241983825 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_224.806369288
Short name T964
Test name
Test status
Simulation time 200189986490 ps
CPU time 2555 seconds
Started Jul 25 05:14:24 PM PDT 24
Finished Jul 25 05:57:00 PM PDT 24
Peak memory 392468 kb
Host smart-43164024-628d-471b-9821-3371a119fa28
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=806369288 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_224.806369288 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_256.764432273
Short name T376
Test name
Test status
Simulation time 97697142287 ps
CPU time 2261.24 seconds
Started Jul 25 05:14:24 PM PDT 24
Finished Jul 25 05:52:05 PM PDT 24
Peak memory 378608 kb
Host smart-35c68ab1-4f41-4c71-9388-eab898a9cefa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=764432273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_256.764432273 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_384.2084455986
Short name T228
Test name
Test status
Simulation time 62602789021 ps
CPU time 1502.72 seconds
Started Jul 25 05:14:28 PM PDT 24
Finished Jul 25 05:39:31 PM PDT 24
Peak memory 342476 kb
Host smart-27db7960-96ec-4aff-a1c6-d73ca59b8476
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2084455986 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_384.2084455986 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_512.3340285949
Short name T729
Test name
Test status
Simulation time 465863208939 ps
CPU time 1389.29 seconds
Started Jul 25 05:14:24 PM PDT 24
Finished Jul 25 05:37:33 PM PDT 24
Peak memory 297396 kb
Host smart-369458da-7e75-46ec-ab02-d4e74012247b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3340285949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_512.3340285949 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_shake_128.1872663761
Short name T440
Test name
Test status
Simulation time 125388087723 ps
CPU time 5073.88 seconds
Started Jul 25 05:14:27 PM PDT 24
Finished Jul 25 06:39:01 PM PDT 24
Peak memory 668636 kb
Host smart-bf4c0181-ca59-4f10-ac2a-44d4f3cf44a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1872663761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_128.1872663761 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_shake_256.2622977899
Short name T428
Test name
Test status
Simulation time 152893718738 ps
CPU time 4652.22 seconds
Started Jul 25 05:14:25 PM PDT 24
Finished Jul 25 06:31:58 PM PDT 24
Peak memory 571816 kb
Host smart-d469a109-71a8-422f-9186-898cc492190b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2622977899 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_256.2622977899 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/23.kmac_alert_test.2433865961
Short name T389
Test name
Test status
Simulation time 14541193 ps
CPU time 0.88 seconds
Started Jul 25 05:14:36 PM PDT 24
Finished Jul 25 05:14:37 PM PDT 24
Peak memory 218212 kb
Host smart-9f200555-3e2a-4b52-a182-76b6bfd4957a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433865961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.2433865961 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_alert_test/latest

Test location /workspace/coverage/default/23.kmac_app.2348371595
Short name T184
Test name
Test status
Simulation time 9379813014 ps
CPU time 209.59 seconds
Started Jul 25 05:14:36 PM PDT 24
Finished Jul 25 05:18:05 PM PDT 24
Peak memory 241116 kb
Host smart-ea4fd7f4-0eff-4aec-9cac-e426aad9a8e1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348371595 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.2348371595 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/23.kmac_app/latest

Test location /workspace/coverage/default/23.kmac_burst_write.1582025226
Short name T433
Test name
Test status
Simulation time 18365548939 ps
CPU time 500.74 seconds
Started Jul 25 05:14:34 PM PDT 24
Finished Jul 25 05:22:55 PM PDT 24
Peak memory 232024 kb
Host smart-c6414d2b-0594-4989-8bc1-a3ea6217c719
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582025226 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.158202522
6 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_burst_write/latest

Test location /workspace/coverage/default/23.kmac_entropy_refresh.2244747844
Short name T978
Test name
Test status
Simulation time 2372850630 ps
CPU time 171.96 seconds
Started Jul 25 05:14:36 PM PDT 24
Finished Jul 25 05:17:28 PM PDT 24
Peak memory 243024 kb
Host smart-3797427a-756b-4b4c-a224-d45ef5ce9e5d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244747844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.2
244747844 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/23.kmac_error.3342612068
Short name T175
Test name
Test status
Simulation time 5615411123 ps
CPU time 162.04 seconds
Started Jul 25 05:14:35 PM PDT 24
Finished Jul 25 05:17:17 PM PDT 24
Peak memory 257688 kb
Host smart-2293e403-f7f0-411f-89e0-d33617fec34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342612068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.3342612068 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_error/latest

Test location /workspace/coverage/default/23.kmac_key_error.2452577733
Short name T777
Test name
Test status
Simulation time 900153707 ps
CPU time 7.11 seconds
Started Jul 25 05:14:35 PM PDT 24
Finished Jul 25 05:14:42 PM PDT 24
Peak memory 223324 kb
Host smart-e93c2e80-33df-4c2d-96f7-f8ec9f6c3b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452577733 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.2452577733 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_key_error/latest

Test location /workspace/coverage/default/23.kmac_lc_escalation.661887389
Short name T1002
Test name
Test status
Simulation time 142573689 ps
CPU time 1.46 seconds
Started Jul 25 05:14:37 PM PDT 24
Finished Jul 25 05:14:39 PM PDT 24
Peak memory 226616 kb
Host smart-252bb6e4-88bb-450f-86b1-cfabb46ad6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661887389 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.661887389 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/23.kmac_lc_escalation/latest

Test location /workspace/coverage/default/23.kmac_long_msg_and_output.3811192381
Short name T806
Test name
Test status
Simulation time 84168204310 ps
CPU time 2316.55 seconds
Started Jul 25 05:14:36 PM PDT 24
Finished Jul 25 05:53:13 PM PDT 24
Peak memory 405684 kb
Host smart-aed38e78-7855-4e05-abdd-ece651dd033e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811192381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_a
nd_output.3811192381 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/23.kmac_sideload.3294580970
Short name T374
Test name
Test status
Simulation time 9756316603 ps
CPU time 222.56 seconds
Started Jul 25 05:14:34 PM PDT 24
Finished Jul 25 05:18:17 PM PDT 24
Peak memory 240084 kb
Host smart-ff32db47-4ea6-4c35-915f-68eb4f10ba9b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294580970 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.3294580970 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_sideload/latest

Test location /workspace/coverage/default/23.kmac_smoke.935551325
Short name T962
Test name
Test status
Simulation time 2147728245 ps
CPU time 27.84 seconds
Started Jul 25 05:14:24 PM PDT 24
Finished Jul 25 05:14:52 PM PDT 24
Peak memory 226460 kb
Host smart-04d43efe-372f-4759-9c18-da73b34caba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935551325 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.935551325 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_smoke/latest

Test location /workspace/coverage/default/23.kmac_stress_all.3144883162
Short name T842
Test name
Test status
Simulation time 5440811957 ps
CPU time 48.48 seconds
Started Jul 25 05:14:39 PM PDT 24
Finished Jul 25 05:15:27 PM PDT 24
Peak memory 240260 kb
Host smart-08dec79e-dbc0-4409-9f50-be0cc2ab8e52
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3144883162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.3144883162 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_stress_all/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_kmac.3257906020
Short name T639
Test name
Test status
Simulation time 278969163 ps
CPU time 6.17 seconds
Started Jul 25 05:14:38 PM PDT 24
Finished Jul 25 05:14:45 PM PDT 24
Peak memory 218532 kb
Host smart-9e77c080-1bae-4cea-afd9-b78833fcbb58
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257906020 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.kmac_test_vectors_kmac.3257906020 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_kmac_xof.2437644237
Short name T637
Test name
Test status
Simulation time 176726464 ps
CPU time 5.33 seconds
Started Jul 25 05:14:37 PM PDT 24
Finished Jul 25 05:14:42 PM PDT 24
Peak memory 218612 kb
Host smart-3e369767-46f3-4f5e-8bfd-5fd67ad20470
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437644237 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.kmac_test_vectors_kmac_xof.2437644237 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_224.652645853
Short name T211
Test name
Test status
Simulation time 21352297965 ps
CPU time 2031.04 seconds
Started Jul 25 05:14:35 PM PDT 24
Finished Jul 25 05:48:26 PM PDT 24
Peak memory 402892 kb
Host smart-169ee22e-8c8b-4947-b2fa-e7e7a07d6eaa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=652645853 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_224.652645853 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_256.3249248144
Short name T487
Test name
Test status
Simulation time 36941711330 ps
CPU time 1776.65 seconds
Started Jul 25 05:14:35 PM PDT 24
Finished Jul 25 05:44:12 PM PDT 24
Peak memory 385784 kb
Host smart-255598ff-37bd-47eb-8a3b-940680012076
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3249248144 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_256.3249248144 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_384.1778907085
Short name T743
Test name
Test status
Simulation time 94482742234 ps
CPU time 1630.29 seconds
Started Jul 25 05:14:36 PM PDT 24
Finished Jul 25 05:41:46 PM PDT 24
Peak memory 338452 kb
Host smart-83212afd-4e12-489d-b83a-8e499b63af07
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1778907085 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_384.1778907085 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_512.2483174119
Short name T128
Test name
Test status
Simulation time 21637947490 ps
CPU time 1152.76 seconds
Started Jul 25 05:14:40 PM PDT 24
Finished Jul 25 05:33:53 PM PDT 24
Peak memory 302016 kb
Host smart-baee1a69-db04-4402-83f4-f37d561c1b4d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2483174119 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_512.2483174119 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_shake_128.2540630765
Short name T393
Test name
Test status
Simulation time 531398352699 ps
CPU time 6147.6 seconds
Started Jul 25 05:14:35 PM PDT 24
Finished Jul 25 06:57:03 PM PDT 24
Peak memory 638228 kb
Host smart-af4cb4e6-6562-438f-a262-50850ba79f2b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2540630765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_128.2540630765 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_shake_256.812787238
Short name T537
Test name
Test status
Simulation time 231107378894 ps
CPU time 5172.77 seconds
Started Jul 25 05:14:38 PM PDT 24
Finished Jul 25 06:40:52 PM PDT 24
Peak memory 570716 kb
Host smart-fc079598-c6e9-49a1-b270-5f32fb5e5cf1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=812787238 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_256.812787238 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/24.kmac_alert_test.338221043
Short name T931
Test name
Test status
Simulation time 18810765 ps
CPU time 0.81 seconds
Started Jul 25 05:14:52 PM PDT 24
Finished Jul 25 05:14:53 PM PDT 24
Peak memory 218228 kb
Host smart-fe472cfd-ad5c-455c-b7bf-f94ac8514d0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338221043 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.338221043 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/24.kmac_alert_test/latest

Test location /workspace/coverage/default/24.kmac_app.2644158461
Short name T753
Test name
Test status
Simulation time 17688836306 ps
CPU time 362.01 seconds
Started Jul 25 05:14:51 PM PDT 24
Finished Jul 25 05:20:53 PM PDT 24
Peak memory 251292 kb
Host smart-a371850f-1ead-44eb-84c8-0fb61ad4bea4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644158461 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.2644158461 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/24.kmac_app/latest

Test location /workspace/coverage/default/24.kmac_burst_write.1678066860
Short name T638
Test name
Test status
Simulation time 33917710362 ps
CPU time 411.92 seconds
Started Jul 25 05:14:51 PM PDT 24
Finished Jul 25 05:21:43 PM PDT 24
Peak memory 231340 kb
Host smart-b9e38d92-715a-496a-bbe0-4d90b7c56102
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678066860 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.167806686
0 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_burst_write/latest

Test location /workspace/coverage/default/24.kmac_entropy_refresh.670394507
Short name T20
Test name
Test status
Simulation time 20379328842 ps
CPU time 248.61 seconds
Started Jul 25 05:14:51 PM PDT 24
Finished Jul 25 05:19:00 PM PDT 24
Peak memory 245892 kb
Host smart-e0baafc9-bcd8-4795-8cee-ab3001c9d88f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670394507 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.67
0394507 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/24.kmac_error.1643257383
Short name T223
Test name
Test status
Simulation time 53898033360 ps
CPU time 138.25 seconds
Started Jul 25 05:14:48 PM PDT 24
Finished Jul 25 05:17:07 PM PDT 24
Peak memory 251232 kb
Host smart-f179d90c-8d3b-4efd-b256-0ddeb01a357b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643257383 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.1643257383 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_error/latest

Test location /workspace/coverage/default/24.kmac_key_error.3531158462
Short name T994
Test name
Test status
Simulation time 4819797671 ps
CPU time 6.27 seconds
Started Jul 25 05:14:48 PM PDT 24
Finished Jul 25 05:14:54 PM PDT 24
Peak memory 223340 kb
Host smart-d6cbc769-ee38-44ad-b050-f061e1878409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531158462 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.3531158462 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_key_error/latest

Test location /workspace/coverage/default/24.kmac_long_msg_and_output.942609930
Short name T214
Test name
Test status
Simulation time 54375933224 ps
CPU time 1408.8 seconds
Started Jul 25 05:14:38 PM PDT 24
Finished Jul 25 05:38:08 PM PDT 24
Peak memory 345508 kb
Host smart-6330ab50-2d6d-4a33-a59f-bcad9f26de2f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942609930 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_an
d_output.942609930 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/24.kmac_sideload.2541818318
Short name T901
Test name
Test status
Simulation time 7184978688 ps
CPU time 117.06 seconds
Started Jul 25 05:14:41 PM PDT 24
Finished Jul 25 05:16:38 PM PDT 24
Peak memory 241516 kb
Host smart-040e0af3-2915-4e75-89f5-0277dcef4ff1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541818318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.2541818318 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_sideload/latest

Test location /workspace/coverage/default/24.kmac_smoke.3511146224
Short name T301
Test name
Test status
Simulation time 19463295564 ps
CPU time 79.8 seconds
Started Jul 25 05:14:35 PM PDT 24
Finished Jul 25 05:15:55 PM PDT 24
Peak memory 226564 kb
Host smart-0d09b443-2619-4fff-85fe-c52b79f85416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511146224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.3511146224 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_smoke/latest

Test location /workspace/coverage/default/24.kmac_stress_all.2407772781
Short name T699
Test name
Test status
Simulation time 44276728758 ps
CPU time 755.99 seconds
Started Jul 25 05:14:47 PM PDT 24
Finished Jul 25 05:27:23 PM PDT 24
Peak memory 321284 kb
Host smart-f7e411d1-4a9b-4253-becf-6761b556cbb5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2407772781 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.2407772781 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_stress_all/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_kmac.3526091096
Short name T304
Test name
Test status
Simulation time 1835774224 ps
CPU time 5.9 seconds
Started Jul 25 05:14:51 PM PDT 24
Finished Jul 25 05:14:57 PM PDT 24
Peak memory 218464 kb
Host smart-65482255-2516-42b4-b8d8-7b07c6ba490e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526091096 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.kmac_test_vectors_kmac.3526091096 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_kmac_xof.653524554
Short name T455
Test name
Test status
Simulation time 224848076 ps
CPU time 6.38 seconds
Started Jul 25 05:14:46 PM PDT 24
Finished Jul 25 05:14:52 PM PDT 24
Peak memory 219436 kb
Host smart-9841652f-e49e-4f77-aa1b-8f235338ab04
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653524554 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.kmac_test_vectors_kmac_xof.653524554 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_224.2848437187
Short name T767
Test name
Test status
Simulation time 24821280178 ps
CPU time 2200.83 seconds
Started Jul 25 05:14:51 PM PDT 24
Finished Jul 25 05:51:33 PM PDT 24
Peak memory 403036 kb
Host smart-aeb689a8-0ad3-4a9a-87ac-cb321d08664e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2848437187 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_224.2848437187 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_256.2918724919
Short name T219
Test name
Test status
Simulation time 80307749981 ps
CPU time 1932.04 seconds
Started Jul 25 05:14:48 PM PDT 24
Finished Jul 25 05:47:00 PM PDT 24
Peak memory 387996 kb
Host smart-88f37155-938d-47e2-b047-783293e17210
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2918724919 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_256.2918724919 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_384.3256064924
Short name T268
Test name
Test status
Simulation time 15758218121 ps
CPU time 1520.29 seconds
Started Jul 25 05:14:47 PM PDT 24
Finished Jul 25 05:40:07 PM PDT 24
Peak memory 343724 kb
Host smart-11388cf7-6570-49ff-a5ab-0c465d1d9329
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3256064924 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_384.3256064924 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_512.1034665742
Short name T409
Test name
Test status
Simulation time 10446301057 ps
CPU time 1185.04 seconds
Started Jul 25 05:14:46 PM PDT 24
Finished Jul 25 05:34:32 PM PDT 24
Peak memory 299536 kb
Host smart-a2794ee6-ef19-4a16-a031-9b411e52a668
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1034665742 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_512.1034665742 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_shake_128.4266100188
Short name T524
Test name
Test status
Simulation time 333240159085 ps
CPU time 4903.02 seconds
Started Jul 25 05:14:48 PM PDT 24
Finished Jul 25 06:36:32 PM PDT 24
Peak memory 646844 kb
Host smart-235d74e4-31a7-4482-8baf-af98e184d334
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4266100188 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_128.4266100188 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_shake_256.1477236000
Short name T957
Test name
Test status
Simulation time 621683267915 ps
CPU time 4410.72 seconds
Started Jul 25 05:14:45 PM PDT 24
Finished Jul 25 06:28:16 PM PDT 24
Peak memory 564112 kb
Host smart-5a618da3-8762-44d6-ac03-f91afe622db9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1477236000 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_256.1477236000 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/25.kmac_alert_test.558106566
Short name T388
Test name
Test status
Simulation time 13905556 ps
CPU time 0.82 seconds
Started Jul 25 05:14:56 PM PDT 24
Finished Jul 25 05:14:57 PM PDT 24
Peak memory 218232 kb
Host smart-a51a8494-0f0c-4420-a617-8ece861f64d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558106566 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.558106566 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/25.kmac_alert_test/latest

Test location /workspace/coverage/default/25.kmac_app.751204479
Short name T1007
Test name
Test status
Simulation time 85823194269 ps
CPU time 375.43 seconds
Started Jul 25 05:14:58 PM PDT 24
Finished Jul 25 05:21:13 PM PDT 24
Peak memory 248068 kb
Host smart-ea42e7ef-c3c9-452f-915c-f4d664fe0c80
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751204479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.751204479 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/25.kmac_app/latest

Test location /workspace/coverage/default/25.kmac_burst_write.1124275810
Short name T514
Test name
Test status
Simulation time 78925121436 ps
CPU time 969.69 seconds
Started Jul 25 05:14:48 PM PDT 24
Finished Jul 25 05:30:58 PM PDT 24
Peak memory 236316 kb
Host smart-adbde504-0332-40e0-a835-801e9b8f753a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124275810 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.112427581
0 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_burst_write/latest

Test location /workspace/coverage/default/25.kmac_entropy_refresh.1342297325
Short name T754
Test name
Test status
Simulation time 16475297596 ps
CPU time 105.21 seconds
Started Jul 25 05:15:00 PM PDT 24
Finished Jul 25 05:16:45 PM PDT 24
Peak memory 233400 kb
Host smart-5c8a219a-fb6a-4d29-83ca-e8409ad12035
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342297325 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.1
342297325 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/25.kmac_error.2590056781
Short name T999
Test name
Test status
Simulation time 33547923526 ps
CPU time 214.67 seconds
Started Jul 25 05:15:01 PM PDT 24
Finished Jul 25 05:18:36 PM PDT 24
Peak memory 258884 kb
Host smart-1be2241c-b88b-415d-aa27-fb8f5966c7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590056781 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.2590056781 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_error/latest

Test location /workspace/coverage/default/25.kmac_key_error.406612146
Short name T118
Test name
Test status
Simulation time 904824485 ps
CPU time 4.92 seconds
Started Jul 25 05:14:58 PM PDT 24
Finished Jul 25 05:15:03 PM PDT 24
Peak memory 222768 kb
Host smart-89a24070-7994-40ac-ab76-27aba3b4864b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406612146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.406612146 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_key_error/latest

Test location /workspace/coverage/default/25.kmac_long_msg_and_output.477025826
Short name T153
Test name
Test status
Simulation time 149055891710 ps
CPU time 1268.26 seconds
Started Jul 25 05:14:52 PM PDT 24
Finished Jul 25 05:36:00 PM PDT 24
Peak memory 320356 kb
Host smart-3b830934-659f-4442-9a6a-7ba006eefe00
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477025826 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_an
d_output.477025826 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/25.kmac_sideload.3469906241
Short name T527
Test name
Test status
Simulation time 900934808 ps
CPU time 76.42 seconds
Started Jul 25 05:14:50 PM PDT 24
Finished Jul 25 05:16:07 PM PDT 24
Peak memory 228400 kb
Host smart-d776b10e-6ef2-4fb3-bf23-78fd28823d1c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469906241 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.3469906241 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_sideload/latest

Test location /workspace/coverage/default/25.kmac_smoke.662916300
Short name T1015
Test name
Test status
Simulation time 12062130290 ps
CPU time 72.08 seconds
Started Jul 25 05:14:46 PM PDT 24
Finished Jul 25 05:15:59 PM PDT 24
Peak memory 226652 kb
Host smart-c9908262-c0f2-4568-8d53-6b1bff2d3c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662916300 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.662916300 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_smoke/latest

Test location /workspace/coverage/default/25.kmac_stress_all.2121653212
Short name T985
Test name
Test status
Simulation time 52383226794 ps
CPU time 1346.6 seconds
Started Jul 25 05:15:00 PM PDT 24
Finished Jul 25 05:37:27 PM PDT 24
Peak memory 354760 kb
Host smart-c5c36cb5-9087-4dd3-80e6-2395caa69a30
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2121653212 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.2121653212 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_stress_all/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_kmac.2297202892
Short name T401
Test name
Test status
Simulation time 262982070 ps
CPU time 6.08 seconds
Started Jul 25 05:14:47 PM PDT 24
Finished Jul 25 05:14:54 PM PDT 24
Peak memory 218692 kb
Host smart-41c7cd6d-afc0-47aa-a01d-6650ffb865a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297202892 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.kmac_test_vectors_kmac.2297202892 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_kmac_xof.3701076185
Short name T799
Test name
Test status
Simulation time 414579258 ps
CPU time 6.49 seconds
Started Jul 25 05:14:48 PM PDT 24
Finished Jul 25 05:14:55 PM PDT 24
Peak memory 218512 kb
Host smart-132cd073-6adc-4fe8-a287-b74bebecb40b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701076185 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.kmac_test_vectors_kmac_xof.3701076185 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_224.1958600054
Short name T816
Test name
Test status
Simulation time 142662787455 ps
CPU time 2361.28 seconds
Started Jul 25 05:14:53 PM PDT 24
Finished Jul 25 05:54:15 PM PDT 24
Peak memory 411208 kb
Host smart-7fbfb3e9-00ee-4ebf-a01a-c6345c3f1d94
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1958600054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_224.1958600054 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_256.1267597057
Short name T582
Test name
Test status
Simulation time 1156986814686 ps
CPU time 2351.57 seconds
Started Jul 25 05:14:50 PM PDT 24
Finished Jul 25 05:54:02 PM PDT 24
Peak memory 389484 kb
Host smart-57c0d00d-15c0-4640-89f4-8dd2b35df62c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1267597057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_256.1267597057 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_384.3474688220
Short name T533
Test name
Test status
Simulation time 67553208605 ps
CPU time 1433.29 seconds
Started Jul 25 05:14:48 PM PDT 24
Finished Jul 25 05:38:42 PM PDT 24
Peak memory 334124 kb
Host smart-06c791f3-af54-4d59-b8f0-369dad84f80b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3474688220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_384.3474688220 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_512.1325641725
Short name T246
Test name
Test status
Simulation time 131054891059 ps
CPU time 1299.24 seconds
Started Jul 25 05:14:51 PM PDT 24
Finished Jul 25 05:36:31 PM PDT 24
Peak memory 297060 kb
Host smart-93a0f637-c406-4c2f-8c10-31295895a2d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1325641725 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_512.1325641725 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_shake_128.574223424
Short name T1021
Test name
Test status
Simulation time 3204446071743 ps
CPU time 5678.3 seconds
Started Jul 25 05:14:48 PM PDT 24
Finished Jul 25 06:49:27 PM PDT 24
Peak memory 643216 kb
Host smart-ef068f6f-ceb8-4f57-92fb-f6870280eac8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=574223424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_128.574223424 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_shake_256.2242594618
Short name T564
Test name
Test status
Simulation time 305276043258 ps
CPU time 4844.64 seconds
Started Jul 25 05:14:47 PM PDT 24
Finished Jul 25 06:35:33 PM PDT 24
Peak memory 558576 kb
Host smart-8be18f4e-aa78-408f-9aea-d86fae5213f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2242594618 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_256.2242594618 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/26.kmac_alert_test.2993366586
Short name T465
Test name
Test status
Simulation time 34404218 ps
CPU time 0.8 seconds
Started Jul 25 05:15:01 PM PDT 24
Finished Jul 25 05:15:02 PM PDT 24
Peak memory 218236 kb
Host smart-6b9dae6d-f326-43cd-983a-f91c8f3c4a8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993366586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.2993366586 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_alert_test/latest

Test location /workspace/coverage/default/26.kmac_app.550529762
Short name T810
Test name
Test status
Simulation time 3985264897 ps
CPU time 21.05 seconds
Started Jul 25 05:14:57 PM PDT 24
Finished Jul 25 05:15:18 PM PDT 24
Peak memory 226776 kb
Host smart-0bba088a-7426-4ce5-a2d8-0d57bbd9b431
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550529762 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.550529762 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/26.kmac_app/latest

Test location /workspace/coverage/default/26.kmac_burst_write.1564207877
Short name T497
Test name
Test status
Simulation time 138972233521 ps
CPU time 1072.09 seconds
Started Jul 25 05:14:58 PM PDT 24
Finished Jul 25 05:32:50 PM PDT 24
Peak memory 238844 kb
Host smart-62325aa5-7972-44dd-8164-43848adccb1f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564207877 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.156420787
7 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_burst_write/latest

Test location /workspace/coverage/default/26.kmac_entropy_refresh.1175601705
Short name T906
Test name
Test status
Simulation time 8563277771 ps
CPU time 357.3 seconds
Started Jul 25 05:14:59 PM PDT 24
Finished Jul 25 05:20:56 PM PDT 24
Peak memory 251352 kb
Host smart-23c628c3-ed5d-43ca-9b35-8dc6bcbe83d4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175601705 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.1
175601705 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/26.kmac_error.1165013244
Short name T691
Test name
Test status
Simulation time 1789781795 ps
CPU time 24.46 seconds
Started Jul 25 05:14:57 PM PDT 24
Finished Jul 25 05:15:22 PM PDT 24
Peak memory 240772 kb
Host smart-9a11a378-ede2-4452-b75d-9b35e92cca04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165013244 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.1165013244 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_error/latest

Test location /workspace/coverage/default/26.kmac_key_error.3090708595
Short name T989
Test name
Test status
Simulation time 1830355724 ps
CPU time 7.35 seconds
Started Jul 25 05:14:58 PM PDT 24
Finished Jul 25 05:15:05 PM PDT 24
Peak memory 223388 kb
Host smart-2bdb6749-a1b9-46e7-b573-8d86b833a6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090708595 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.3090708595 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_key_error/latest

Test location /workspace/coverage/default/26.kmac_lc_escalation.2136518384
Short name T14
Test name
Test status
Simulation time 44053757 ps
CPU time 1.4 seconds
Started Jul 25 05:14:56 PM PDT 24
Finished Jul 25 05:14:57 PM PDT 24
Peak memory 226580 kb
Host smart-a07ea561-4cb7-4123-8adc-4fa0e0fdd896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136518384 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.2136518384 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/26.kmac_lc_escalation/latest

Test location /workspace/coverage/default/26.kmac_long_msg_and_output.233842298
Short name T209
Test name
Test status
Simulation time 289395138736 ps
CPU time 1820.16 seconds
Started Jul 25 05:14:58 PM PDT 24
Finished Jul 25 05:45:18 PM PDT 24
Peak memory 380996 kb
Host smart-db67cd2b-f979-45d1-ae3b-16d620aba904
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233842298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_an
d_output.233842298 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/26.kmac_sideload.200684187
Short name T108
Test name
Test status
Simulation time 958782325 ps
CPU time 17.18 seconds
Started Jul 25 05:14:57 PM PDT 24
Finished Jul 25 05:15:15 PM PDT 24
Peak memory 225308 kb
Host smart-dc704307-7d1e-49c1-81b7-d0161e74797e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200684187 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.200684187 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_sideload/latest

Test location /workspace/coverage/default/26.kmac_smoke.3859149213
Short name T773
Test name
Test status
Simulation time 2609729230 ps
CPU time 49.96 seconds
Started Jul 25 05:15:01 PM PDT 24
Finished Jul 25 05:15:51 PM PDT 24
Peak memory 226512 kb
Host smart-0eb9bc03-631c-45b8-a9fa-4940d3e2a49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859149213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.3859149213 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_smoke/latest

Test location /workspace/coverage/default/26.kmac_stress_all.4157962960
Short name T66
Test name
Test status
Simulation time 28321439410 ps
CPU time 594.25 seconds
Started Jul 25 05:15:00 PM PDT 24
Finished Jul 25 05:24:54 PM PDT 24
Peak memory 303036 kb
Host smart-eec5e802-024c-44b0-846c-4f58e17dc7f3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4157962960 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.4157962960 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_stress_all/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_kmac.2369196826
Short name T308
Test name
Test status
Simulation time 602131478 ps
CPU time 5.36 seconds
Started Jul 25 05:15:00 PM PDT 24
Finished Jul 25 05:15:06 PM PDT 24
Peak memory 218556 kb
Host smart-cd4ff966-ae80-4144-9eda-fa1f3b9aad47
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369196826 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.kmac_test_vectors_kmac.2369196826 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_kmac_xof.3173083690
Short name T930
Test name
Test status
Simulation time 1482869709 ps
CPU time 7.79 seconds
Started Jul 25 05:14:58 PM PDT 24
Finished Jul 25 05:15:06 PM PDT 24
Peak memory 218700 kb
Host smart-d394b60d-6981-4ecc-98f2-db1a37768432
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173083690 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.kmac_test_vectors_kmac_xof.3173083690 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_224.935979667
Short name T617
Test name
Test status
Simulation time 38795949914 ps
CPU time 2043.72 seconds
Started Jul 25 05:14:58 PM PDT 24
Finished Jul 25 05:49:02 PM PDT 24
Peak memory 395216 kb
Host smart-0e1b5453-1c30-434c-a526-50c903338350
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=935979667 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_224.935979667 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_256.1160695830
Short name T218
Test name
Test status
Simulation time 99528142170 ps
CPU time 2143.48 seconds
Started Jul 25 05:14:56 PM PDT 24
Finished Jul 25 05:50:40 PM PDT 24
Peak memory 382312 kb
Host smart-9eef3ed6-1547-42d8-9632-20852abf4b44
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1160695830 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_256.1160695830 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_384.3004907753
Short name T875
Test name
Test status
Simulation time 63771342272 ps
CPU time 1471.2 seconds
Started Jul 25 05:14:57 PM PDT 24
Finished Jul 25 05:39:29 PM PDT 24
Peak memory 335404 kb
Host smart-bbc27e1b-4abb-41cb-b249-91767b6c7965
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3004907753 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_384.3004907753 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_512.1841346991
Short name T439
Test name
Test status
Simulation time 107542753986 ps
CPU time 1288.58 seconds
Started Jul 25 05:15:01 PM PDT 24
Finished Jul 25 05:36:30 PM PDT 24
Peak memory 301888 kb
Host smart-f933bc66-7e6c-411b-a7d1-b421fa16704d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1841346991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_512.1841346991 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_shake_128.2238775317
Short name T359
Test name
Test status
Simulation time 176236904025 ps
CPU time 5233.51 seconds
Started Jul 25 05:15:00 PM PDT 24
Finished Jul 25 06:42:14 PM PDT 24
Peak memory 643736 kb
Host smart-e3743d9e-40e0-4f4c-a6cc-95020af1ec5a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2238775317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_128.2238775317 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_shake_256.3940743625
Short name T239
Test name
Test status
Simulation time 382211993650 ps
CPU time 4970.8 seconds
Started Jul 25 05:15:03 PM PDT 24
Finished Jul 25 06:37:54 PM PDT 24
Peak memory 567744 kb
Host smart-61d6c900-5491-4942-ae77-fdc532cd2d4a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3940743625 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_256.3940743625 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/27.kmac_alert_test.852203105
Short name T903
Test name
Test status
Simulation time 14578293 ps
CPU time 0.81 seconds
Started Jul 25 05:15:15 PM PDT 24
Finished Jul 25 05:15:16 PM PDT 24
Peak memory 218268 kb
Host smart-606a0008-d28e-4eab-a691-aecf0b06e6e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852203105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.852203105 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/27.kmac_alert_test/latest

Test location /workspace/coverage/default/27.kmac_app.3801624869
Short name T890
Test name
Test status
Simulation time 16552830441 ps
CPU time 140.57 seconds
Started Jul 25 05:15:05 PM PDT 24
Finished Jul 25 05:17:26 PM PDT 24
Peak memory 234536 kb
Host smart-633db76e-7339-433d-9b7f-150ca0799667
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801624869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.3801624869 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/27.kmac_app/latest

Test location /workspace/coverage/default/27.kmac_burst_write.2962929911
Short name T578
Test name
Test status
Simulation time 33769094401 ps
CPU time 1131.08 seconds
Started Jul 25 05:14:58 PM PDT 24
Finished Jul 25 05:33:49 PM PDT 24
Peak memory 238904 kb
Host smart-ccee8c00-c3a4-4946-a9a3-506d47f575d3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962929911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.296292991
1 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_burst_write/latest

Test location /workspace/coverage/default/27.kmac_entropy_refresh.81277915
Short name T84
Test name
Test status
Simulation time 7081735052 ps
CPU time 255.62 seconds
Started Jul 25 05:15:04 PM PDT 24
Finished Jul 25 05:19:19 PM PDT 24
Peak memory 244868 kb
Host smart-189a2671-8866-4bb4-8d75-8bd69bce01f3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81277915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.812
77915 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/27.kmac_error.4037663989
Short name T824
Test name
Test status
Simulation time 36955379599 ps
CPU time 378.29 seconds
Started Jul 25 05:15:05 PM PDT 24
Finished Jul 25 05:21:24 PM PDT 24
Peak memory 251700 kb
Host smart-f26344ad-8db4-40cf-b021-bbb154b88e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037663989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.4037663989 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_error/latest

Test location /workspace/coverage/default/27.kmac_lc_escalation.167318757
Short name T87
Test name
Test status
Simulation time 52517459 ps
CPU time 1.41 seconds
Started Jul 25 05:15:05 PM PDT 24
Finished Jul 25 05:15:07 PM PDT 24
Peak memory 226700 kb
Host smart-4044971a-d8af-40f1-b862-73936896c040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167318757 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.167318757 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/27.kmac_lc_escalation/latest

Test location /workspace/coverage/default/27.kmac_long_msg_and_output.621730187
Short name T1008
Test name
Test status
Simulation time 61829911255 ps
CPU time 2311.35 seconds
Started Jul 25 05:15:03 PM PDT 24
Finished Jul 25 05:53:35 PM PDT 24
Peak memory 401660 kb
Host smart-42a5b11a-daa3-491f-8dea-be0d61ab5012
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621730187 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_an
d_output.621730187 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/27.kmac_sideload.3508644791
Short name T615
Test name
Test status
Simulation time 4196989950 ps
CPU time 120.43 seconds
Started Jul 25 05:14:58 PM PDT 24
Finished Jul 25 05:16:59 PM PDT 24
Peak memory 233224 kb
Host smart-58d509a8-871e-4fe1-a3d5-ec3e9d3fcb0f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508644791 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.3508644791 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_sideload/latest

Test location /workspace/coverage/default/27.kmac_smoke.3768348839
Short name T274
Test name
Test status
Simulation time 30139695605 ps
CPU time 77.53 seconds
Started Jul 25 05:14:59 PM PDT 24
Finished Jul 25 05:16:17 PM PDT 24
Peak memory 223628 kb
Host smart-75051eef-25b7-45db-969f-b320833bbf64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768348839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.3768348839 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_smoke/latest

Test location /workspace/coverage/default/27.kmac_stress_all.4208665322
Short name T61
Test name
Test status
Simulation time 1015620562 ps
CPU time 93.02 seconds
Started Jul 25 05:15:08 PM PDT 24
Finished Jul 25 05:16:42 PM PDT 24
Peak memory 243232 kb
Host smart-1b4b2ddf-cf67-43a7-b289-1df0d01f2c22
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4208665322 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.4208665322 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_stress_all/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_kmac.2251437043
Short name T1039
Test name
Test status
Simulation time 115580936 ps
CPU time 6.2 seconds
Started Jul 25 05:15:08 PM PDT 24
Finished Jul 25 05:15:14 PM PDT 24
Peak memory 218552 kb
Host smart-3d1c0fcb-120b-40bc-8427-7dd5671530b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251437043 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.kmac_test_vectors_kmac.2251437043 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_kmac_xof.2746199213
Short name T870
Test name
Test status
Simulation time 1106194368 ps
CPU time 6.02 seconds
Started Jul 25 05:15:06 PM PDT 24
Finished Jul 25 05:15:12 PM PDT 24
Peak memory 218576 kb
Host smart-db870ead-a1da-4263-a488-cf7574288c2e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746199213 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.kmac_test_vectors_kmac_xof.2746199213 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_224.3378029647
Short name T658
Test name
Test status
Simulation time 83960567103 ps
CPU time 2160.71 seconds
Started Jul 25 05:15:05 PM PDT 24
Finished Jul 25 05:51:06 PM PDT 24
Peak memory 387532 kb
Host smart-7a451956-dcfb-4edb-a4a3-f853f575282a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3378029647 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_224.3378029647 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_256.2696586610
Short name T608
Test name
Test status
Simulation time 771639232412 ps
CPU time 2458.05 seconds
Started Jul 25 05:15:07 PM PDT 24
Finished Jul 25 05:56:05 PM PDT 24
Peak memory 386016 kb
Host smart-b31a36a2-e582-44b8-9116-0363ca21881a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2696586610 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_256.2696586610 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_384.1833420561
Short name T981
Test name
Test status
Simulation time 65336310277 ps
CPU time 1615.25 seconds
Started Jul 25 05:15:05 PM PDT 24
Finished Jul 25 05:42:00 PM PDT 24
Peak memory 338192 kb
Host smart-701200d2-9c78-4800-844b-53d22062a046
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1833420561 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_384.1833420561 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_512.113176741
Short name T384
Test name
Test status
Simulation time 114457646269 ps
CPU time 1352.86 seconds
Started Jul 25 05:15:08 PM PDT 24
Finished Jul 25 05:37:42 PM PDT 24
Peak memory 300272 kb
Host smart-6cc97a2d-6356-4f6f-89d0-797e5434d93f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=113176741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_512.113176741 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_shake_128.3966899666
Short name T379
Test name
Test status
Simulation time 191312047731 ps
CPU time 5554.67 seconds
Started Jul 25 05:15:05 PM PDT 24
Finished Jul 25 06:47:41 PM PDT 24
Peak memory 674532 kb
Host smart-b134bfe8-a64b-4dba-99f2-fcb4b76defc9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3966899666 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_128.3966899666 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_shake_256.548914783
Short name T1064
Test name
Test status
Simulation time 884699480550 ps
CPU time 4405.63 seconds
Started Jul 25 05:15:03 PM PDT 24
Finished Jul 25 06:28:29 PM PDT 24
Peak memory 571816 kb
Host smart-4359c195-0d1e-4762-8b3e-64bd7d73aed5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=548914783 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_256.548914783 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/28.kmac_alert_test.2921283512
Short name T480
Test name
Test status
Simulation time 30217686 ps
CPU time 0.9 seconds
Started Jul 25 05:15:26 PM PDT 24
Finished Jul 25 05:15:27 PM PDT 24
Peak memory 218252 kb
Host smart-c6560df8-9403-4c54-979a-9d7e355aa3c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921283512 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.2921283512 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_alert_test/latest

Test location /workspace/coverage/default/28.kmac_burst_write.2507545526
Short name T159
Test name
Test status
Simulation time 27073358172 ps
CPU time 645.11 seconds
Started Jul 25 05:15:15 PM PDT 24
Finished Jul 25 05:26:01 PM PDT 24
Peak memory 233088 kb
Host smart-3bd6aba9-1341-4427-8c43-af4eb6bcdec7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507545526 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.250754552
6 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_burst_write/latest

Test location /workspace/coverage/default/28.kmac_entropy_refresh.1729032552
Short name T19
Test name
Test status
Simulation time 290989756 ps
CPU time 5.36 seconds
Started Jul 25 05:15:23 PM PDT 24
Finished Jul 25 05:15:28 PM PDT 24
Peak memory 218472 kb
Host smart-9df9811e-2e2b-4c5f-9594-e1a9a3a0868b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729032552 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.1
729032552 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/28.kmac_error.2774904937
Short name T673
Test name
Test status
Simulation time 28552804710 ps
CPU time 449.14 seconds
Started Jul 25 05:15:23 PM PDT 24
Finished Jul 25 05:22:53 PM PDT 24
Peak memory 274660 kb
Host smart-01da3ac3-4ec6-433c-a0fd-8e7f0f893dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774904937 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.2774904937 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_error/latest

Test location /workspace/coverage/default/28.kmac_key_error.1153144162
Short name T1058
Test name
Test status
Simulation time 224110537 ps
CPU time 2.3 seconds
Started Jul 25 05:15:25 PM PDT 24
Finished Jul 25 05:15:28 PM PDT 24
Peak memory 222292 kb
Host smart-5a8293b8-84d7-4847-83db-7d9fe594e188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153144162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.1153144162 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_key_error/latest

Test location /workspace/coverage/default/28.kmac_lc_escalation.1521946692
Short name T55
Test name
Test status
Simulation time 56693234 ps
CPU time 1.5 seconds
Started Jul 25 05:15:24 PM PDT 24
Finished Jul 25 05:15:25 PM PDT 24
Peak memory 226616 kb
Host smart-b58443d7-5c1c-46a0-a742-386db11bd376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521946692 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.1521946692 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/28.kmac_lc_escalation/latest

Test location /workspace/coverage/default/28.kmac_long_msg_and_output.3190402170
Short name T954
Test name
Test status
Simulation time 104824524893 ps
CPU time 2766.87 seconds
Started Jul 25 05:15:18 PM PDT 24
Finished Jul 25 06:01:25 PM PDT 24
Peak memory 453968 kb
Host smart-691fb8b6-8ecc-4419-8527-73d9e005d0ca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190402170 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_a
nd_output.3190402170 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/28.kmac_sideload.9048940
Short name T744
Test name
Test status
Simulation time 24282167169 ps
CPU time 510.5 seconds
Started Jul 25 05:15:15 PM PDT 24
Finished Jul 25 05:23:46 PM PDT 24
Peak memory 258060 kb
Host smart-2329bb1b-79d9-46b8-b7ac-961a75d28750
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9048940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.9048940 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_sideload/latest

Test location /workspace/coverage/default/28.kmac_smoke.1577851628
Short name T329
Test name
Test status
Simulation time 76080528 ps
CPU time 1.06 seconds
Started Jul 25 05:15:14 PM PDT 24
Finished Jul 25 05:15:15 PM PDT 24
Peak memory 218492 kb
Host smart-cb5a5bad-fe0d-45b3-899a-f97a707656bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577851628 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.1577851628 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_smoke/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_kmac.1657189887
Short name T231
Test name
Test status
Simulation time 373661919 ps
CPU time 5.96 seconds
Started Jul 25 05:15:12 PM PDT 24
Finished Jul 25 05:15:18 PM PDT 24
Peak memory 219500 kb
Host smart-ba46083b-2e0c-4e06-b64d-c8deb5854821
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657189887 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.kmac_test_vectors_kmac.1657189887 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_kmac_xof.1486301491
Short name T206
Test name
Test status
Simulation time 218632372 ps
CPU time 6.27 seconds
Started Jul 25 05:15:24 PM PDT 24
Finished Jul 25 05:15:31 PM PDT 24
Peak memory 218692 kb
Host smart-fb5e830b-eea4-4bb1-9424-e73405ea91ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486301491 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.kmac_test_vectors_kmac_xof.1486301491 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_224.514478406
Short name T469
Test name
Test status
Simulation time 93150559998 ps
CPU time 1976.43 seconds
Started Jul 25 05:15:15 PM PDT 24
Finished Jul 25 05:48:11 PM PDT 24
Peak memory 394632 kb
Host smart-494d36cf-8004-44a0-8e1d-62a969e0b2a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=514478406 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_224.514478406 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_256.1437775938
Short name T475
Test name
Test status
Simulation time 37692994127 ps
CPU time 1911 seconds
Started Jul 25 05:15:14 PM PDT 24
Finished Jul 25 05:47:06 PM PDT 24
Peak memory 387832 kb
Host smart-8e374163-7ec3-4146-a74a-13b3ccfb7d85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1437775938 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_256.1437775938 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_384.3900939657
Short name T391
Test name
Test status
Simulation time 103991346494 ps
CPU time 1626.25 seconds
Started Jul 25 05:15:15 PM PDT 24
Finished Jul 25 05:42:21 PM PDT 24
Peak memory 342432 kb
Host smart-d73f57f4-89c4-4b38-94d7-aba2e12aa92c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3900939657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_384.3900939657 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_512.1771143394
Short name T835
Test name
Test status
Simulation time 170616472850 ps
CPU time 1245.44 seconds
Started Jul 25 05:15:16 PM PDT 24
Finished Jul 25 05:36:02 PM PDT 24
Peak memory 300608 kb
Host smart-7b527818-3c9e-470d-a858-45609ddc37fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1771143394 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_512.1771143394 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_shake_128.2481314442
Short name T551
Test name
Test status
Simulation time 226759942338 ps
CPU time 5452.28 seconds
Started Jul 25 05:15:15 PM PDT 24
Finished Jul 25 06:46:08 PM PDT 24
Peak memory 661064 kb
Host smart-dd853628-93ef-4a47-8195-5196c121ab64
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2481314442 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_128.2481314442 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_shake_256.431938709
Short name T203
Test name
Test status
Simulation time 1571899989163 ps
CPU time 5699.57 seconds
Started Jul 25 05:15:14 PM PDT 24
Finished Jul 25 06:50:14 PM PDT 24
Peak memory 574956 kb
Host smart-9e57b30b-0ab5-4c60-8497-339e433a768f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=431938709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_256.431938709 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/29.kmac_alert_test.2957778198
Short name T279
Test name
Test status
Simulation time 59653613 ps
CPU time 0.87 seconds
Started Jul 25 05:15:36 PM PDT 24
Finished Jul 25 05:15:37 PM PDT 24
Peak memory 218284 kb
Host smart-fe1ea611-8018-43df-adb2-4ccd6eafbeae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957778198 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.2957778198 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_alert_test/latest

Test location /workspace/coverage/default/29.kmac_app.2369590551
Short name T520
Test name
Test status
Simulation time 22846353836 ps
CPU time 170.85 seconds
Started Jul 25 05:15:35 PM PDT 24
Finished Jul 25 05:18:26 PM PDT 24
Peak memory 237840 kb
Host smart-ee671aba-7649-450f-8834-010ca7cd9607
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369590551 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.2369590551 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/29.kmac_app/latest

Test location /workspace/coverage/default/29.kmac_burst_write.1678535298
Short name T569
Test name
Test status
Simulation time 189749544481 ps
CPU time 1138.01 seconds
Started Jul 25 05:15:24 PM PDT 24
Finished Jul 25 05:34:23 PM PDT 24
Peak memory 237036 kb
Host smart-e67412e2-a175-40d7-b472-f18adc93978d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678535298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.167853529
8 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_burst_write/latest

Test location /workspace/coverage/default/29.kmac_entropy_refresh.3519361765
Short name T734
Test name
Test status
Simulation time 22824228781 ps
CPU time 144.38 seconds
Started Jul 25 05:15:35 PM PDT 24
Finished Jul 25 05:17:59 PM PDT 24
Peak memory 238316 kb
Host smart-6394c13f-f3fd-4633-850f-534ec1ac1b10
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519361765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.3
519361765 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/29.kmac_error.1797576286
Short name T1048
Test name
Test status
Simulation time 8246582710 ps
CPU time 144.14 seconds
Started Jul 25 05:15:36 PM PDT 24
Finished Jul 25 05:18:00 PM PDT 24
Peak memory 251284 kb
Host smart-7b6801f4-c82e-491d-b393-47a5d2bf084e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797576286 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.1797576286 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_error/latest

Test location /workspace/coverage/default/29.kmac_lc_escalation.2892452100
Short name T861
Test name
Test status
Simulation time 46526282 ps
CPU time 1.32 seconds
Started Jul 25 05:15:32 PM PDT 24
Finished Jul 25 05:15:34 PM PDT 24
Peak memory 226624 kb
Host smart-aa10065e-6486-4037-80dc-d6102c4e4860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892452100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.2892452100 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/29.kmac_lc_escalation/latest

Test location /workspace/coverage/default/29.kmac_long_msg_and_output.1048700191
Short name T528
Test name
Test status
Simulation time 105558419741 ps
CPU time 2101.66 seconds
Started Jul 25 05:15:23 PM PDT 24
Finished Jul 25 05:50:25 PM PDT 24
Peak memory 393448 kb
Host smart-560470b1-796e-4c90-b039-0df00fcf6a97
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048700191 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_a
nd_output.1048700191 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/29.kmac_sideload.3575526201
Short name T625
Test name
Test status
Simulation time 40843569033 ps
CPU time 400.87 seconds
Started Jul 25 05:15:23 PM PDT 24
Finished Jul 25 05:22:05 PM PDT 24
Peak memory 253688 kb
Host smart-e6571d8b-ac7c-46c1-b154-949dbd88afd5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575526201 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.3575526201 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_sideload/latest

Test location /workspace/coverage/default/29.kmac_smoke.492295066
Short name T741
Test name
Test status
Simulation time 9332611896 ps
CPU time 70.55 seconds
Started Jul 25 05:15:24 PM PDT 24
Finished Jul 25 05:16:34 PM PDT 24
Peak memory 226652 kb
Host smart-c761e6e2-c811-4511-9a14-8341f6e21439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492295066 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.492295066 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_smoke/latest

Test location /workspace/coverage/default/29.kmac_stress_all.3542529943
Short name T313
Test name
Test status
Simulation time 34321740942 ps
CPU time 909.02 seconds
Started Jul 25 05:15:32 PM PDT 24
Finished Jul 25 05:30:41 PM PDT 24
Peak memory 319260 kb
Host smart-abf1f6ff-5831-49c5-94f4-f32982822729
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3542529943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.3542529943 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_stress_all/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_kmac.2754242906
Short name T688
Test name
Test status
Simulation time 343994728 ps
CPU time 6.03 seconds
Started Jul 25 05:15:33 PM PDT 24
Finished Jul 25 05:15:39 PM PDT 24
Peak memory 218612 kb
Host smart-f117ff75-7248-4d09-b8fd-6c44aa330057
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754242906 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.kmac_test_vectors_kmac.2754242906 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_kmac_xof.3025398128
Short name T624
Test name
Test status
Simulation time 254080157 ps
CPU time 6.41 seconds
Started Jul 25 05:15:33 PM PDT 24
Finished Jul 25 05:15:39 PM PDT 24
Peak memory 218520 kb
Host smart-5099aa37-69c1-4cc8-af49-f9dcf2e70876
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025398128 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.kmac_test_vectors_kmac_xof.3025398128 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_224.2723400919
Short name T111
Test name
Test status
Simulation time 113693534962 ps
CPU time 1937.35 seconds
Started Jul 25 05:15:24 PM PDT 24
Finished Jul 25 05:47:42 PM PDT 24
Peak memory 399892 kb
Host smart-26743329-8a79-4f5d-946f-712c1c40eb37
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2723400919 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_224.2723400919 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_256.1780444134
Short name T251
Test name
Test status
Simulation time 84793510630 ps
CPU time 2208.77 seconds
Started Jul 25 05:15:25 PM PDT 24
Finished Jul 25 05:52:14 PM PDT 24
Peak memory 394300 kb
Host smart-e72e78ba-3e19-4239-9b51-9d75f510fafa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1780444134 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_256.1780444134 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_384.875989608
Short name T911
Test name
Test status
Simulation time 194174302142 ps
CPU time 1746.35 seconds
Started Jul 25 05:15:32 PM PDT 24
Finished Jul 25 05:44:39 PM PDT 24
Peak memory 346148 kb
Host smart-60b34bfa-298c-4d60-aa9f-d4f14f0a4eff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=875989608 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_384.875989608 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_512.597530596
Short name T714
Test name
Test status
Simulation time 139155775656 ps
CPU time 1373.11 seconds
Started Jul 25 05:15:32 PM PDT 24
Finished Jul 25 05:38:26 PM PDT 24
Peak memory 301648 kb
Host smart-91348d53-638a-4f7c-8de3-d2a68053f853
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=597530596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_512.597530596 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_shake_128.2367626901
Short name T38
Test name
Test status
Simulation time 829127778895 ps
CPU time 5683.09 seconds
Started Jul 25 05:15:35 PM PDT 24
Finished Jul 25 06:50:19 PM PDT 24
Peak memory 639580 kb
Host smart-e510d23f-2ca4-4f2f-962d-4b33deb272b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2367626901 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_128.2367626901 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_shake_256.553077459
Short name T1028
Test name
Test status
Simulation time 107570337628 ps
CPU time 3991.87 seconds
Started Jul 25 05:15:34 PM PDT 24
Finished Jul 25 06:22:06 PM PDT 24
Peak memory 563452 kb
Host smart-7a4602f1-eb21-43b8-96d4-624b65887ffc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=553077459 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_256.553077459 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/3.kmac_alert_test.206395438
Short name T350
Test name
Test status
Simulation time 28688615 ps
CPU time 0.99 seconds
Started Jul 25 05:12:13 PM PDT 24
Finished Jul 25 05:12:15 PM PDT 24
Peak memory 218232 kb
Host smart-7f31db17-2953-44e2-9357-78af93de0c5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206395438 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.206395438 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/3.kmac_alert_test/latest

Test location /workspace/coverage/default/3.kmac_burst_write.3798767574
Short name T1033
Test name
Test status
Simulation time 200460838582 ps
CPU time 1206.87 seconds
Started Jul 25 05:12:16 PM PDT 24
Finished Jul 25 05:32:23 PM PDT 24
Peak memory 237196 kb
Host smart-663fecd8-ad99-4743-b1ed-948b9fd919c0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798767574 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.3798767574
+enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_burst_write/latest

Test location /workspace/coverage/default/3.kmac_edn_timeout_error.3449182592
Short name T725
Test name
Test status
Simulation time 37285703 ps
CPU time 1 seconds
Started Jul 25 05:12:13 PM PDT 24
Finished Jul 25 05:12:14 PM PDT 24
Peak memory 218268 kb
Host smart-7908f0f4-67f6-4a20-8af9-6dd56b00f629
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3449182592 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.3449182592 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_mode_error.3771348551
Short name T1009
Test name
Test status
Simulation time 55011823 ps
CPU time 0.95 seconds
Started Jul 25 05:12:14 PM PDT 24
Finished Jul 25 05:12:15 PM PDT 24
Peak memory 221476 kb
Host smart-ae247c44-f3e4-4d85-8bf9-8ca769e653a3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3771348551 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.3771348551 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_ready_error.3062611188
Short name T679
Test name
Test status
Simulation time 13967988067 ps
CPU time 71.62 seconds
Started Jul 25 05:12:15 PM PDT 24
Finished Jul 25 05:13:27 PM PDT 24
Peak memory 220728 kb
Host smart-a4e4583b-0155-49e3-9b2c-906ea291807e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062611188 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.3062611188 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_refresh.3637687136
Short name T366
Test name
Test status
Simulation time 1654667949 ps
CPU time 78.98 seconds
Started Jul 25 05:12:11 PM PDT 24
Finished Jul 25 05:13:30 PM PDT 24
Peak memory 230652 kb
Host smart-63b02ed8-a028-4d45-b212-8f70db5dbcc6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637687136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.36
37687136 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/3.kmac_error.1617178869
Short name T927
Test name
Test status
Simulation time 20506295310 ps
CPU time 441.19 seconds
Started Jul 25 05:12:16 PM PDT 24
Finished Jul 25 05:19:37 PM PDT 24
Peak memory 267588 kb
Host smart-0f7249c6-0ba8-4ba2-b365-a42a56395b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617178869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.1617178869 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_error/latest

Test location /workspace/coverage/default/3.kmac_key_error.3960480332
Short name T626
Test name
Test status
Simulation time 679976238 ps
CPU time 7.65 seconds
Started Jul 25 05:12:17 PM PDT 24
Finished Jul 25 05:12:25 PM PDT 24
Peak memory 224528 kb
Host smart-b800cff4-891f-4b77-8bd1-98049d12e6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960480332 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.3960480332 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_key_error/latest

Test location /workspace/coverage/default/3.kmac_lc_escalation.547008423
Short name T918
Test name
Test status
Simulation time 471895047 ps
CPU time 24.65 seconds
Started Jul 25 05:12:11 PM PDT 24
Finished Jul 25 05:12:36 PM PDT 24
Peak memory 236480 kb
Host smart-2e25eb54-60d5-4187-987d-96d57b15f09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547008423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.547008423 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_lc_escalation/latest

Test location /workspace/coverage/default/3.kmac_long_msg_and_output.3954069048
Short name T460
Test name
Test status
Simulation time 17510494443 ps
CPU time 1666.59 seconds
Started Jul 25 05:12:15 PM PDT 24
Finished Jul 25 05:40:02 PM PDT 24
Peak memory 358600 kb
Host smart-aec2710d-4a94-424a-832e-fb052079537e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954069048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_an
d_output.3954069048 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/3.kmac_mubi.1558169711
Short name T748
Test name
Test status
Simulation time 2148862074 ps
CPU time 121.58 seconds
Started Jul 25 05:12:17 PM PDT 24
Finished Jul 25 05:14:19 PM PDT 24
Peak memory 233956 kb
Host smart-7fba35cf-d7f8-4197-9ff8-1ebab6b52a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558169711 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.1558169711 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_mubi/latest

Test location /workspace/coverage/default/3.kmac_sec_cm.1098933336
Short name T35
Test name
Test status
Simulation time 63358285260 ps
CPU time 111.42 seconds
Started Jul 25 05:12:14 PM PDT 24
Finished Jul 25 05:14:06 PM PDT 24
Peak memory 260520 kb
Host smart-4aeb046c-d351-4bab-a036-b57b6c3aef04
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098933336 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.1098933336 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/3.kmac_sec_cm/latest

Test location /workspace/coverage/default/3.kmac_sideload.2949522424
Short name T335
Test name
Test status
Simulation time 17440081193 ps
CPU time 375.21 seconds
Started Jul 25 05:12:14 PM PDT 24
Finished Jul 25 05:18:29 PM PDT 24
Peak memory 250968 kb
Host smart-ba684454-03d3-4cb9-bd2f-8b216a9ebb79
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949522424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.2949522424 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_sideload/latest

Test location /workspace/coverage/default/3.kmac_smoke.1827584592
Short name T68
Test name
Test status
Simulation time 54025694675 ps
CPU time 85.84 seconds
Started Jul 25 05:12:14 PM PDT 24
Finished Jul 25 05:13:40 PM PDT 24
Peak memory 226804 kb
Host smart-773a429e-282a-4ff4-b791-db0bfd057180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827584592 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.1827584592 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_smoke/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac.924367853
Short name T414
Test name
Test status
Simulation time 427821507 ps
CPU time 5.71 seconds
Started Jul 25 05:12:15 PM PDT 24
Finished Jul 25 05:12:21 PM PDT 24
Peak memory 218572 kb
Host smart-1ef43b2e-e522-4cdd-b86d-e1184aac3082
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924367853 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.kmac_test_vectors_kmac.924367853 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac_xof.3597983732
Short name T501
Test name
Test status
Simulation time 438664123 ps
CPU time 5.72 seconds
Started Jul 25 05:12:14 PM PDT 24
Finished Jul 25 05:12:20 PM PDT 24
Peak memory 218600 kb
Host smart-c15b68cb-eb40-427e-bc84-60f2a0247a98
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597983732 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.kmac_test_vectors_kmac_xof.3597983732 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_224.456848796
Short name T566
Test name
Test status
Simulation time 100596556006 ps
CPU time 2571.83 seconds
Started Jul 25 05:12:15 PM PDT 24
Finished Jul 25 05:55:07 PM PDT 24
Peak memory 401460 kb
Host smart-b089ed04-40ae-46c5-b0b5-1570167ee786
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=456848796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.456848796 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_256.1060445045
Short name T756
Test name
Test status
Simulation time 90649146655 ps
CPU time 1989.37 seconds
Started Jul 25 05:12:11 PM PDT 24
Finished Jul 25 05:45:21 PM PDT 24
Peak memory 385212 kb
Host smart-5d26c3cf-daf4-4bd2-bcdb-8475564fa18d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1060445045 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.1060445045 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_384.3025800005
Short name T589
Test name
Test status
Simulation time 786087399005 ps
CPU time 1821.89 seconds
Started Jul 25 05:12:13 PM PDT 24
Finished Jul 25 05:42:35 PM PDT 24
Peak memory 342016 kb
Host smart-68515732-8064-4198-be62-cc12d9dc1a36
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3025800005 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.3025800005 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_512.1676002404
Short name T879
Test name
Test status
Simulation time 168674296082 ps
CPU time 1238.53 seconds
Started Jul 25 05:12:12 PM PDT 24
Finished Jul 25 05:32:51 PM PDT 24
Peak memory 303612 kb
Host smart-0491722e-5de8-4210-b9d3-60e760cc3011
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1676002404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.1676002404 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_shake_128.3907676636
Short name T341
Test name
Test status
Simulation time 387899680995 ps
CPU time 5592.97 seconds
Started Jul 25 05:12:12 PM PDT 24
Finished Jul 25 06:45:26 PM PDT 24
Peak memory 664056 kb
Host smart-29d7de7f-1e42-4248-9c96-5cb04c3f3162
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3907676636 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.3907676636 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_shake_256.4279574404
Short name T543
Test name
Test status
Simulation time 220496267081 ps
CPU time 4922.78 seconds
Started Jul 25 05:12:16 PM PDT 24
Finished Jul 25 06:34:20 PM PDT 24
Peak memory 565020 kb
Host smart-0396ac62-98e1-45f0-bbea-b88118e41935
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4279574404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.4279574404 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/30.kmac_alert_test.2234115661
Short name T781
Test name
Test status
Simulation time 13319627 ps
CPU time 0.8 seconds
Started Jul 25 05:15:52 PM PDT 24
Finished Jul 25 05:15:53 PM PDT 24
Peak memory 218236 kb
Host smart-e9dcbb3a-a313-4ae3-89d0-ed4d29ced5a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234115661 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.2234115661 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_alert_test/latest

Test location /workspace/coverage/default/30.kmac_app.986451241
Short name T434
Test name
Test status
Simulation time 4879841131 ps
CPU time 64.72 seconds
Started Jul 25 05:15:51 PM PDT 24
Finished Jul 25 05:16:56 PM PDT 24
Peak memory 230608 kb
Host smart-e0eb9bb4-6cd5-47b2-87b4-5ba6e0b1be05
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986451241 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.986451241 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/30.kmac_app/latest

Test location /workspace/coverage/default/30.kmac_burst_write.704794287
Short name T992
Test name
Test status
Simulation time 10520032229 ps
CPU time 1013.51 seconds
Started Jul 25 05:15:45 PM PDT 24
Finished Jul 25 05:32:39 PM PDT 24
Peak memory 239540 kb
Host smart-fc0c0c75-8ee9-4780-ae66-9224ff3df123
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704794287 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.704794287
+enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_burst_write/latest

Test location /workspace/coverage/default/30.kmac_entropy_refresh.1361857548
Short name T375
Test name
Test status
Simulation time 5464488169 ps
CPU time 155.53 seconds
Started Jul 25 05:15:54 PM PDT 24
Finished Jul 25 05:18:29 PM PDT 24
Peak memory 237680 kb
Host smart-5ee1f48c-a91f-4892-906e-8dfca80a4883
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361857548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.1
361857548 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/30.kmac_error.2872480758
Short name T790
Test name
Test status
Simulation time 34356082014 ps
CPU time 303.07 seconds
Started Jul 25 05:15:54 PM PDT 24
Finished Jul 25 05:20:57 PM PDT 24
Peak memory 256560 kb
Host smart-6d811a4d-7ed1-42af-b3b1-f43bcd15a3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872480758 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.2872480758 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_error/latest

Test location /workspace/coverage/default/30.kmac_key_error.4143104100
Short name T678
Test name
Test status
Simulation time 1305305622 ps
CPU time 10.01 seconds
Started Jul 25 05:15:52 PM PDT 24
Finished Jul 25 05:16:02 PM PDT 24
Peak memory 224008 kb
Host smart-fde95144-f882-49fc-965c-d4ead9533d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143104100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.4143104100 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_key_error/latest

Test location /workspace/coverage/default/30.kmac_lc_escalation.1740594368
Short name T33
Test name
Test status
Simulation time 1056333558 ps
CPU time 7.39 seconds
Started Jul 25 05:15:52 PM PDT 24
Finished Jul 25 05:15:59 PM PDT 24
Peak memory 226660 kb
Host smart-993f3ef1-f0ce-4489-9a9e-676ebdb4f0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740594368 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.1740594368 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/30.kmac_lc_escalation/latest

Test location /workspace/coverage/default/30.kmac_long_msg_and_output.3878691332
Short name T222
Test name
Test status
Simulation time 11832527749 ps
CPU time 78.01 seconds
Started Jul 25 05:15:43 PM PDT 24
Finished Jul 25 05:17:01 PM PDT 24
Peak memory 225752 kb
Host smart-91967938-c14d-4c45-a7df-c5c03e97b879
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878691332 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_a
nd_output.3878691332 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/30.kmac_sideload.1576913363
Short name T672
Test name
Test status
Simulation time 1851287405 ps
CPU time 14.94 seconds
Started Jul 25 05:15:42 PM PDT 24
Finished Jul 25 05:15:57 PM PDT 24
Peak memory 219568 kb
Host smart-f852fb15-39d2-4552-9392-04d0cfbecdc8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576913363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.1576913363 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_sideload/latest

Test location /workspace/coverage/default/30.kmac_smoke.2219015358
Short name T952
Test name
Test status
Simulation time 7577140252 ps
CPU time 89.05 seconds
Started Jul 25 05:15:44 PM PDT 24
Finished Jul 25 05:17:13 PM PDT 24
Peak memory 218640 kb
Host smart-b2f94834-6d21-40bd-b556-efb4a4ff35ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219015358 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.2219015358 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_smoke/latest

Test location /workspace/coverage/default/30.kmac_stress_all.3027655190
Short name T779
Test name
Test status
Simulation time 24232339602 ps
CPU time 145.69 seconds
Started Jul 25 05:15:51 PM PDT 24
Finished Jul 25 05:18:17 PM PDT 24
Peak memory 246160 kb
Host smart-e6adb8b8-4b27-4696-95df-e2d418b89228
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3027655190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.3027655190 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_stress_all/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_kmac.3192737438
Short name T385
Test name
Test status
Simulation time 338422413 ps
CPU time 6.41 seconds
Started Jul 25 05:15:43 PM PDT 24
Finished Jul 25 05:15:50 PM PDT 24
Peak memory 218524 kb
Host smart-9a819150-80bb-4258-b05e-6f4a21fd8027
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192737438 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.kmac_test_vectors_kmac.3192737438 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_kmac_xof.370108184
Short name T352
Test name
Test status
Simulation time 420692779 ps
CPU time 5.73 seconds
Started Jul 25 05:15:51 PM PDT 24
Finished Jul 25 05:15:57 PM PDT 24
Peak memory 218528 kb
Host smart-81e2d60a-33ec-45f2-a8df-8f5dce140b9e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370108184 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.kmac_test_vectors_kmac_xof.370108184 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_224.692183777
Short name T502
Test name
Test status
Simulation time 317113811361 ps
CPU time 2302.07 seconds
Started Jul 25 05:15:44 PM PDT 24
Finished Jul 25 05:54:07 PM PDT 24
Peak memory 385552 kb
Host smart-ae63c0c7-06f0-4209-86f0-087f8c2e957f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=692183777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_224.692183777 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_256.704563440
Short name T757
Test name
Test status
Simulation time 188559485445 ps
CPU time 2059.98 seconds
Started Jul 25 05:15:45 PM PDT 24
Finished Jul 25 05:50:05 PM PDT 24
Peak memory 383024 kb
Host smart-3dd6829e-b934-44bf-b565-1e73441940fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=704563440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_256.704563440 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_384.1173502681
Short name T946
Test name
Test status
Simulation time 286063109724 ps
CPU time 1753.65 seconds
Started Jul 25 05:15:42 PM PDT 24
Finished Jul 25 05:44:56 PM PDT 24
Peak memory 343860 kb
Host smart-a969482c-fdfd-4edb-947f-99d75c8b63c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1173502681 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_384.1173502681 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_512.2921435588
Short name T309
Test name
Test status
Simulation time 66494797162 ps
CPU time 1240.65 seconds
Started Jul 25 05:15:41 PM PDT 24
Finished Jul 25 05:36:22 PM PDT 24
Peak memory 301128 kb
Host smart-92c7a20b-af44-4bca-9400-5c46bd51ba45
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2921435588 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_512.2921435588 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_shake_128.1069201853
Short name T238
Test name
Test status
Simulation time 376882164363 ps
CPU time 5206.58 seconds
Started Jul 25 05:15:44 PM PDT 24
Finished Jul 25 06:42:31 PM PDT 24
Peak memory 651972 kb
Host smart-76842636-6271-4577-bf5f-95ca7a8cb4de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1069201853 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_128.1069201853 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_shake_256.1344110695
Short name T435
Test name
Test status
Simulation time 863453255099 ps
CPU time 4974.11 seconds
Started Jul 25 05:15:43 PM PDT 24
Finished Jul 25 06:38:38 PM PDT 24
Peak memory 563968 kb
Host smart-fcc0316f-b720-44a3-8123-f5bd80624cb7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1344110695 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_256.1344110695 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/31.kmac_alert_test.4215874297
Short name T809
Test name
Test status
Simulation time 109379153 ps
CPU time 0.89 seconds
Started Jul 25 05:16:13 PM PDT 24
Finished Jul 25 05:16:14 PM PDT 24
Peak memory 218368 kb
Host smart-dbf8aa46-bd2f-4acd-a821-809cdb8666e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215874297 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.4215874297 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_alert_test/latest

Test location /workspace/coverage/default/31.kmac_app.3493610263
Short name T185
Test name
Test status
Simulation time 6479929591 ps
CPU time 175.86 seconds
Started Jul 25 05:16:01 PM PDT 24
Finished Jul 25 05:18:57 PM PDT 24
Peak memory 240884 kb
Host smart-9013bc6b-05f9-49f1-bfbe-51d2b0f6cd2a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493610263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.3493610263 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/31.kmac_app/latest

Test location /workspace/coverage/default/31.kmac_burst_write.3117730203
Short name T474
Test name
Test status
Simulation time 65533607201 ps
CPU time 1866.21 seconds
Started Jul 25 05:15:51 PM PDT 24
Finished Jul 25 05:46:58 PM PDT 24
Peak memory 239592 kb
Host smart-eb65c7c6-9b07-4880-b76f-75afd2915fcc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117730203 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.311773020
3 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_burst_write/latest

Test location /workspace/coverage/default/31.kmac_entropy_refresh.2850916886
Short name T262
Test name
Test status
Simulation time 3474406749 ps
CPU time 168.9 seconds
Started Jul 25 05:16:03 PM PDT 24
Finished Jul 25 05:18:52 PM PDT 24
Peak memory 238336 kb
Host smart-b51be84f-6dfb-4222-b6da-729b74b3d6d1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850916886 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.2
850916886 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/31.kmac_error.276007564
Short name T174
Test name
Test status
Simulation time 15246626650 ps
CPU time 108.92 seconds
Started Jul 25 05:16:03 PM PDT 24
Finished Jul 25 05:17:52 PM PDT 24
Peak memory 243032 kb
Host smart-57b76c0e-3615-4ebe-ab03-5ca75833ea9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276007564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.276007564 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_error/latest

Test location /workspace/coverage/default/31.kmac_key_error.92159068
Short name T675
Test name
Test status
Simulation time 1006980923 ps
CPU time 7.57 seconds
Started Jul 25 05:16:02 PM PDT 24
Finished Jul 25 05:16:10 PM PDT 24
Peak memory 223872 kb
Host smart-ec218a3a-3ba5-44b5-bf7c-a822e499ade7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92159068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.92159068 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_key_error/latest

Test location /workspace/coverage/default/31.kmac_lc_escalation.3281931942
Short name T47
Test name
Test status
Simulation time 2371809714 ps
CPU time 14.35 seconds
Started Jul 25 05:16:02 PM PDT 24
Finished Jul 25 05:16:17 PM PDT 24
Peak memory 234952 kb
Host smart-1c79891a-1943-4a32-ba58-5ab116674360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281931942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.3281931942 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/31.kmac_lc_escalation/latest

Test location /workspace/coverage/default/31.kmac_long_msg_and_output.3809078177
Short name T392
Test name
Test status
Simulation time 23255207629 ps
CPU time 844.56 seconds
Started Jul 25 05:15:54 PM PDT 24
Finished Jul 25 05:29:59 PM PDT 24
Peak memory 288876 kb
Host smart-fb74feac-c6ab-4c4f-87e5-9259d4eb7e14
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809078177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_a
nd_output.3809078177 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/31.kmac_sideload.1244732510
Short name T282
Test name
Test status
Simulation time 42489461771 ps
CPU time 360.84 seconds
Started Jul 25 05:15:51 PM PDT 24
Finished Jul 25 05:21:52 PM PDT 24
Peak memory 254660 kb
Host smart-fe8d3cd0-535e-434c-8bb3-1ecb250d33b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244732510 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.1244732510 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_sideload/latest

Test location /workspace/coverage/default/31.kmac_smoke.3000756582
Short name T372
Test name
Test status
Simulation time 3722138476 ps
CPU time 12.32 seconds
Started Jul 25 05:15:50 PM PDT 24
Finished Jul 25 05:16:02 PM PDT 24
Peak memory 226688 kb
Host smart-fa2a2bd7-8c3b-4ff6-a749-b2e61a15acbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000756582 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.3000756582 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_smoke/latest

Test location /workspace/coverage/default/31.kmac_stress_all.3280126525
Short name T477
Test name
Test status
Simulation time 10162544699 ps
CPU time 831.51 seconds
Started Jul 25 05:16:04 PM PDT 24
Finished Jul 25 05:29:55 PM PDT 24
Peak memory 317188 kb
Host smart-5849ea01-eec0-481b-b2c2-1ab99e8f8ae1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3280126525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.3280126525 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_stress_all/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_kmac.2030605078
Short name T621
Test name
Test status
Simulation time 115800648 ps
CPU time 6.03 seconds
Started Jul 25 05:16:01 PM PDT 24
Finished Jul 25 05:16:08 PM PDT 24
Peak memory 218532 kb
Host smart-5eefef87-e30a-4a97-ab1a-1d0011ec6cb2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030605078 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.kmac_test_vectors_kmac.2030605078 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_kmac_xof.633221426
Short name T531
Test name
Test status
Simulation time 101262266 ps
CPU time 5.16 seconds
Started Jul 25 05:16:02 PM PDT 24
Finished Jul 25 05:16:07 PM PDT 24
Peak memory 218552 kb
Host smart-ab4463a4-a6c6-46a1-bc1f-3c89760669a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633221426 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.kmac_test_vectors_kmac_xof.633221426 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_224.4047896772
Short name T641
Test name
Test status
Simulation time 65381239975 ps
CPU time 1969.24 seconds
Started Jul 25 05:16:03 PM PDT 24
Finished Jul 25 05:48:52 PM PDT 24
Peak memory 380664 kb
Host smart-42b8c254-9c95-4f5b-b119-cf741c27c564
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4047896772 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_224.4047896772 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_256.4273396989
Short name T252
Test name
Test status
Simulation time 132355289327 ps
CPU time 1994.12 seconds
Started Jul 25 05:16:01 PM PDT 24
Finished Jul 25 05:49:16 PM PDT 24
Peak memory 385884 kb
Host smart-9a0a8947-ebc3-4ecb-8893-a9200171aa8f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4273396989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_256.4273396989 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_384.2765552911
Short name T939
Test name
Test status
Simulation time 213317082127 ps
CPU time 1607 seconds
Started Jul 25 05:16:00 PM PDT 24
Finished Jul 25 05:42:48 PM PDT 24
Peak memory 342844 kb
Host smart-0da9a6e8-cfe7-44e4-ada8-6477d1fca4c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2765552911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_384.2765552911 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_512.1869337231
Short name T1051
Test name
Test status
Simulation time 180922997755 ps
CPU time 1151.4 seconds
Started Jul 25 05:16:00 PM PDT 24
Finished Jul 25 05:35:12 PM PDT 24
Peak memory 296092 kb
Host smart-4822e0e2-4acc-47d2-9b5a-3bf62e580c94
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1869337231 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_512.1869337231 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_shake_128.3149583673
Short name T318
Test name
Test status
Simulation time 318314707009 ps
CPU time 5101.09 seconds
Started Jul 25 05:16:02 PM PDT 24
Finished Jul 25 06:41:04 PM PDT 24
Peak memory 674016 kb
Host smart-672f0d68-108b-461a-bcf0-43deaf13f734
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3149583673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_128.3149583673 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_shake_256.3817468893
Short name T112
Test name
Test status
Simulation time 223692053831 ps
CPU time 4297.73 seconds
Started Jul 25 05:16:01 PM PDT 24
Finished Jul 25 06:27:39 PM PDT 24
Peak memory 568664 kb
Host smart-eca3fa16-8799-4095-bcf9-0ad90d83a6aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3817468893 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_256.3817468893 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/32.kmac_alert_test.810117033
Short name T482
Test name
Test status
Simulation time 76170233 ps
CPU time 0.86 seconds
Started Jul 25 05:16:22 PM PDT 24
Finished Jul 25 05:16:23 PM PDT 24
Peak memory 218324 kb
Host smart-ef134ed5-fc08-488c-b1ed-2b312d0973a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810117033 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.810117033 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/32.kmac_alert_test/latest

Test location /workspace/coverage/default/32.kmac_app.1707464907
Short name T127
Test name
Test status
Simulation time 8659287399 ps
CPU time 57.44 seconds
Started Jul 25 05:16:23 PM PDT 24
Finished Jul 25 05:17:20 PM PDT 24
Peak memory 228844 kb
Host smart-c6f91d95-d766-4316-9532-12d797bcfdbb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707464907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.1707464907 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/32.kmac_app/latest

Test location /workspace/coverage/default/32.kmac_burst_write.2087631062
Short name T354
Test name
Test status
Simulation time 10694255391 ps
CPU time 269.74 seconds
Started Jul 25 05:16:14 PM PDT 24
Finished Jul 25 05:20:44 PM PDT 24
Peak memory 237508 kb
Host smart-b9244a70-2d6a-43bf-a669-df0ad5ebcd16
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087631062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.208763106
2 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_burst_write/latest

Test location /workspace/coverage/default/32.kmac_entropy_refresh.2801740323
Short name T407
Test name
Test status
Simulation time 20154089537 ps
CPU time 409.23 seconds
Started Jul 25 05:16:21 PM PDT 24
Finished Jul 25 05:23:10 PM PDT 24
Peak memory 251388 kb
Host smart-caa1255f-69f4-4300-a1a6-cf7f94a2205d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801740323 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.2
801740323 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/32.kmac_error.1747604863
Short name T265
Test name
Test status
Simulation time 820266139 ps
CPU time 61.24 seconds
Started Jul 25 05:16:21 PM PDT 24
Finished Jul 25 05:17:22 PM PDT 24
Peak memory 239100 kb
Host smart-09871ade-840b-4f6f-922e-eca39f8278c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747604863 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.1747604863 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_error/latest

Test location /workspace/coverage/default/32.kmac_key_error.1160846684
Short name T1074
Test name
Test status
Simulation time 3030157608 ps
CPU time 11.16 seconds
Started Jul 25 05:16:21 PM PDT 24
Finished Jul 25 05:16:32 PM PDT 24
Peak memory 225212 kb
Host smart-57bd8973-2bb2-428c-8569-050af01a13f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160846684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.1160846684 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_key_error/latest

Test location /workspace/coverage/default/32.kmac_lc_escalation.3967720362
Short name T801
Test name
Test status
Simulation time 65860296 ps
CPU time 1.22 seconds
Started Jul 25 05:16:22 PM PDT 24
Finished Jul 25 05:16:23 PM PDT 24
Peak memory 226620 kb
Host smart-7d2ddf47-99e6-41c2-ac88-428b25e69b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967720362 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.3967720362 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/32.kmac_lc_escalation/latest

Test location /workspace/coverage/default/32.kmac_long_msg_and_output.2340051768
Short name T221
Test name
Test status
Simulation time 89710716821 ps
CPU time 2355.51 seconds
Started Jul 25 05:16:13 PM PDT 24
Finished Jul 25 05:55:29 PM PDT 24
Peak memory 427992 kb
Host smart-c7a30637-21a9-4a49-a04d-9c45aad34754
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340051768 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_a
nd_output.2340051768 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/32.kmac_sideload.2248996538
Short name T1067
Test name
Test status
Simulation time 264167669 ps
CPU time 4.63 seconds
Started Jul 25 05:16:14 PM PDT 24
Finished Jul 25 05:16:18 PM PDT 24
Peak memory 220404 kb
Host smart-b137a17b-a35e-4192-b977-123047d5523c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248996538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.2248996538 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_sideload/latest

Test location /workspace/coverage/default/32.kmac_smoke.4197747476
Short name T390
Test name
Test status
Simulation time 5380521264 ps
CPU time 57.63 seconds
Started Jul 25 05:16:12 PM PDT 24
Finished Jul 25 05:17:09 PM PDT 24
Peak memory 226632 kb
Host smart-f9d1f000-6e7f-4c7a-ba83-a2c1cde82770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197747476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.4197747476 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_smoke/latest

Test location /workspace/coverage/default/32.kmac_stress_all.728763542
Short name T506
Test name
Test status
Simulation time 578654752 ps
CPU time 14.6 seconds
Started Jul 25 05:16:22 PM PDT 24
Finished Jul 25 05:16:37 PM PDT 24
Peak memory 226668 kb
Host smart-2017a5cb-c43b-444c-8b6f-600539f2887e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=728763542 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.728763542 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_stress_all/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_kmac.1496799387
Short name T448
Test name
Test status
Simulation time 120287911 ps
CPU time 6.14 seconds
Started Jul 25 05:16:21 PM PDT 24
Finished Jul 25 05:16:27 PM PDT 24
Peak memory 218464 kb
Host smart-2ee572c6-6665-49c4-a8ae-ffa46932f926
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496799387 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.kmac_test_vectors_kmac.1496799387 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_kmac_xof.774740286
Short name T143
Test name
Test status
Simulation time 121058972 ps
CPU time 5.82 seconds
Started Jul 25 05:16:21 PM PDT 24
Finished Jul 25 05:16:27 PM PDT 24
Peak memory 218596 kb
Host smart-23022499-dbb6-4fe2-b462-8e48eededed6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774740286 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.kmac_test_vectors_kmac_xof.774740286 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_224.292261956
Short name T208
Test name
Test status
Simulation time 201234069727 ps
CPU time 2409.19 seconds
Started Jul 25 05:16:12 PM PDT 24
Finished Jul 25 05:56:21 PM PDT 24
Peak memory 398100 kb
Host smart-9c2f28ef-2104-4d7d-a01d-0c7a3e703915
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=292261956 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_224.292261956 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_256.4087709426
Short name T783
Test name
Test status
Simulation time 62052810171 ps
CPU time 1885.94 seconds
Started Jul 25 05:16:14 PM PDT 24
Finished Jul 25 05:47:40 PM PDT 24
Peak memory 386256 kb
Host smart-801524ec-6673-482a-b808-a768af5c9374
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4087709426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_256.4087709426 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_384.3521124604
Short name T576
Test name
Test status
Simulation time 84483302860 ps
CPU time 1788.26 seconds
Started Jul 25 05:16:13 PM PDT 24
Finished Jul 25 05:46:02 PM PDT 24
Peak memory 340936 kb
Host smart-2d563688-a611-48dc-83c5-5b7d35d5a884
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3521124604 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_384.3521124604 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_512.1402208895
Short name T1012
Test name
Test status
Simulation time 195790296744 ps
CPU time 1394.6 seconds
Started Jul 25 05:16:14 PM PDT 24
Finished Jul 25 05:39:29 PM PDT 24
Peak memory 299864 kb
Host smart-55896d5e-f573-4459-a06d-abfea2405638
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1402208895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_512.1402208895 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_shake_128.445091362
Short name T710
Test name
Test status
Simulation time 523517116634 ps
CPU time 6052.61 seconds
Started Jul 25 05:16:11 PM PDT 24
Finished Jul 25 06:57:04 PM PDT 24
Peak memory 650032 kb
Host smart-34649962-7a12-4cab-b028-e44ef893c1a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=445091362 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_128.445091362 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_shake_256.2565177745
Short name T667
Test name
Test status
Simulation time 613220780664 ps
CPU time 4719.98 seconds
Started Jul 25 05:16:12 PM PDT 24
Finished Jul 25 06:34:53 PM PDT 24
Peak memory 575924 kb
Host smart-a22728b5-04c3-4828-909a-5cdb85a30883
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2565177745 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_256.2565177745 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/33.kmac_alert_test.4048448297
Short name T804
Test name
Test status
Simulation time 30090499 ps
CPU time 0.85 seconds
Started Jul 25 05:16:48 PM PDT 24
Finished Jul 25 05:16:49 PM PDT 24
Peak memory 218240 kb
Host smart-5a72e0a3-aaae-45f1-b6ef-53c526815b06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048448297 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.4048448297 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_alert_test/latest

Test location /workspace/coverage/default/33.kmac_app.206238040
Short name T296
Test name
Test status
Simulation time 42763148129 ps
CPU time 342.32 seconds
Started Jul 25 05:16:50 PM PDT 24
Finished Jul 25 05:22:32 PM PDT 24
Peak memory 248824 kb
Host smart-ea11bf01-e1eb-4903-9a33-b8442f1aede8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206238040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.206238040 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/33.kmac_app/latest

Test location /workspace/coverage/default/33.kmac_burst_write.3872351191
Short name T43
Test name
Test status
Simulation time 11742783212 ps
CPU time 1002.05 seconds
Started Jul 25 05:16:26 PM PDT 24
Finished Jul 25 05:33:08 PM PDT 24
Peak memory 235340 kb
Host smart-28519402-fd44-48e5-a8db-46bef1189925
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872351191 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.387235119
1 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_burst_write/latest

Test location /workspace/coverage/default/33.kmac_entropy_refresh.2055497001
Short name T446
Test name
Test status
Simulation time 2049623631 ps
CPU time 109.65 seconds
Started Jul 25 05:16:48 PM PDT 24
Finished Jul 25 05:18:38 PM PDT 24
Peak memory 234388 kb
Host smart-2e7b0681-11be-4c65-a401-38051606e524
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055497001 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.2
055497001 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/33.kmac_error.345663499
Short name T340
Test name
Test status
Simulation time 38208394514 ps
CPU time 483.16 seconds
Started Jul 25 05:16:46 PM PDT 24
Finished Jul 25 05:24:49 PM PDT 24
Peak memory 259388 kb
Host smart-1dd15a76-f2aa-45b2-b895-0553c4738c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345663499 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.345663499 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_error/latest

Test location /workspace/coverage/default/33.kmac_key_error.1358348849
Short name T662
Test name
Test status
Simulation time 3697382965 ps
CPU time 5.91 seconds
Started Jul 25 05:16:45 PM PDT 24
Finished Jul 25 05:16:51 PM PDT 24
Peak memory 223888 kb
Host smart-0c0c660c-5114-406f-8ff6-ac0fd0ab3a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358348849 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.1358348849 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_key_error/latest

Test location /workspace/coverage/default/33.kmac_lc_escalation.214540830
Short name T943
Test name
Test status
Simulation time 149020147 ps
CPU time 1.37 seconds
Started Jul 25 05:16:43 PM PDT 24
Finished Jul 25 05:16:45 PM PDT 24
Peak memory 226600 kb
Host smart-a9095573-53f9-41d6-a160-ef20c935ea52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214540830 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.214540830 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/33.kmac_lc_escalation/latest

Test location /workspace/coverage/default/33.kmac_long_msg_and_output.1352956879
Short name T763
Test name
Test status
Simulation time 404226216957 ps
CPU time 2284.08 seconds
Started Jul 25 05:16:24 PM PDT 24
Finished Jul 25 05:54:28 PM PDT 24
Peak memory 409428 kb
Host smart-f7127196-bbd1-42c7-8582-1023225d04d8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352956879 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_a
nd_output.1352956879 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/33.kmac_sideload.2167101215
Short name T529
Test name
Test status
Simulation time 65242949543 ps
CPU time 508.03 seconds
Started Jul 25 05:16:22 PM PDT 24
Finished Jul 25 05:24:51 PM PDT 24
Peak memory 257540 kb
Host smart-94b32903-6a63-4fd9-934d-ea364b11bf2e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167101215 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.2167101215 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_sideload/latest

Test location /workspace/coverage/default/33.kmac_smoke.740942859
Short name T924
Test name
Test status
Simulation time 14119672410 ps
CPU time 52.74 seconds
Started Jul 25 05:16:21 PM PDT 24
Finished Jul 25 05:17:14 PM PDT 24
Peak memory 222756 kb
Host smart-c446024c-5670-45cc-bf03-55e078375866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740942859 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.740942859 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_smoke/latest

Test location /workspace/coverage/default/33.kmac_stress_all.2823277613
Short name T1040
Test name
Test status
Simulation time 36984314750 ps
CPU time 372.12 seconds
Started Jul 25 05:16:46 PM PDT 24
Finished Jul 25 05:22:58 PM PDT 24
Peak memory 259532 kb
Host smart-14299e5e-d070-4976-9ab4-1f8796b3b5ef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2823277613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.2823277613 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_stress_all/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_kmac.864129000
Short name T444
Test name
Test status
Simulation time 746338844 ps
CPU time 6.29 seconds
Started Jul 25 05:16:36 PM PDT 24
Finished Jul 25 05:16:42 PM PDT 24
Peak memory 219400 kb
Host smart-8f42bf2d-5e03-4737-9bc6-b60d3d8e0e31
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864129000 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.kmac_test_vectors_kmac.864129000 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_kmac_xof.1087504774
Short name T1057
Test name
Test status
Simulation time 798215592 ps
CPU time 5.95 seconds
Started Jul 25 05:16:37 PM PDT 24
Finished Jul 25 05:16:43 PM PDT 24
Peak memory 218596 kb
Host smart-ca5b1841-8c6c-463e-9058-0b4ee1ff5043
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087504774 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.kmac_test_vectors_kmac_xof.1087504774 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_224.2741852484
Short name T912
Test name
Test status
Simulation time 187835197064 ps
CPU time 2356.56 seconds
Started Jul 25 05:16:37 PM PDT 24
Finished Jul 25 05:55:54 PM PDT 24
Peak memory 396908 kb
Host smart-c919d456-9c37-447f-b42b-38397964055b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2741852484 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_224.2741852484 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_256.3074627735
Short name T711
Test name
Test status
Simulation time 66199819917 ps
CPU time 1979.36 seconds
Started Jul 25 05:16:38 PM PDT 24
Finished Jul 25 05:49:38 PM PDT 24
Peak memory 388928 kb
Host smart-1662fbfb-4d1d-4115-b428-2dc507d29348
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3074627735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_256.3074627735 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_384.1915930966
Short name T960
Test name
Test status
Simulation time 48700995649 ps
CPU time 1722.29 seconds
Started Jul 25 05:16:34 PM PDT 24
Finished Jul 25 05:45:17 PM PDT 24
Peak memory 340544 kb
Host smart-30ce1480-b5ad-4745-8101-8a8c41cfc156
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1915930966 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_384.1915930966 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_512.2804320393
Short name T682
Test name
Test status
Simulation time 67665097873 ps
CPU time 1220.95 seconds
Started Jul 25 05:16:37 PM PDT 24
Finished Jul 25 05:36:58 PM PDT 24
Peak memory 302644 kb
Host smart-39500fca-115c-4182-b573-0e94d57c5cf5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2804320393 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_512.2804320393 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_shake_128.3440410376
Short name T542
Test name
Test status
Simulation time 746393325450 ps
CPU time 5237.13 seconds
Started Jul 25 05:16:38 PM PDT 24
Finished Jul 25 06:43:56 PM PDT 24
Peak memory 649352 kb
Host smart-f20b5e9e-cf63-48fe-9059-58846c72fa0a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3440410376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_128.3440410376 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_shake_256.3318635842
Short name T776
Test name
Test status
Simulation time 127245020071 ps
CPU time 4454.17 seconds
Started Jul 25 05:16:36 PM PDT 24
Finished Jul 25 06:30:51 PM PDT 24
Peak memory 573416 kb
Host smart-c5e98bae-1247-4a34-bf34-8abd80c9dae9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3318635842 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_256.3318635842 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/34.kmac_alert_test.2527612674
Short name T462
Test name
Test status
Simulation time 19169788 ps
CPU time 0.91 seconds
Started Jul 25 05:16:54 PM PDT 24
Finished Jul 25 05:16:55 PM PDT 24
Peak memory 218264 kb
Host smart-dd4c1165-08c3-435b-bde8-9a4e65537f10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527612674 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.2527612674 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_alert_test/latest

Test location /workspace/coverage/default/34.kmac_app.3862644438
Short name T285
Test name
Test status
Simulation time 4863952163 ps
CPU time 19.47 seconds
Started Jul 25 05:17:01 PM PDT 24
Finished Jul 25 05:17:20 PM PDT 24
Peak memory 226688 kb
Host smart-0143625a-98f1-4c44-83b7-9ba2aa0b1ea0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862644438 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.3862644438 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/34.kmac_app/latest

Test location /workspace/coverage/default/34.kmac_burst_write.576277040
Short name T99
Test name
Test status
Simulation time 53615969227 ps
CPU time 1643.38 seconds
Started Jul 25 05:16:49 PM PDT 24
Finished Jul 25 05:44:13 PM PDT 24
Peak memory 237380 kb
Host smart-025a12cf-e54c-48e4-8bcb-2a1853a9170e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576277040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.576277040
+enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_burst_write/latest

Test location /workspace/coverage/default/34.kmac_entropy_refresh.2939380466
Short name T358
Test name
Test status
Simulation time 4482700424 ps
CPU time 265.76 seconds
Started Jul 25 05:17:01 PM PDT 24
Finished Jul 25 05:21:27 PM PDT 24
Peak memory 248684 kb
Host smart-fe95f501-effe-4e84-9770-02ce605412db
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939380466 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.2
939380466 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/34.kmac_error.425355627
Short name T503
Test name
Test status
Simulation time 30279533149 ps
CPU time 189.73 seconds
Started Jul 25 05:16:52 PM PDT 24
Finished Jul 25 05:20:02 PM PDT 24
Peak memory 251260 kb
Host smart-bf059eae-f139-4abd-8392-61e2dfafa898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425355627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.425355627 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_error/latest

Test location /workspace/coverage/default/34.kmac_key_error.1519245620
Short name T1022
Test name
Test status
Simulation time 150500037 ps
CPU time 1.97 seconds
Started Jul 25 05:17:01 PM PDT 24
Finished Jul 25 05:17:03 PM PDT 24
Peak memory 222696 kb
Host smart-577823eb-d1c0-40a2-bd53-a43899b11f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519245620 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.1519245620 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_key_error/latest

Test location /workspace/coverage/default/34.kmac_lc_escalation.601069205
Short name T103
Test name
Test status
Simulation time 1757702941 ps
CPU time 16.7 seconds
Started Jul 25 05:16:54 PM PDT 24
Finished Jul 25 05:17:10 PM PDT 24
Peak memory 243212 kb
Host smart-af12ef5c-be34-417b-b9c8-55c28dbc2393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601069205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.601069205 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/34.kmac_lc_escalation/latest

Test location /workspace/coverage/default/34.kmac_long_msg_and_output.2808918055
Short name T665
Test name
Test status
Simulation time 49926181533 ps
CPU time 2559.26 seconds
Started Jul 25 05:16:44 PM PDT 24
Finished Jul 25 05:59:24 PM PDT 24
Peak memory 445708 kb
Host smart-3efeb560-8c0a-4774-afd7-6359195ae5d9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808918055 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_a
nd_output.2808918055 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/34.kmac_sideload.2719722651
Short name T473
Test name
Test status
Simulation time 2977063333 ps
CPU time 239.34 seconds
Started Jul 25 05:16:44 PM PDT 24
Finished Jul 25 05:20:44 PM PDT 24
Peak memory 244428 kb
Host smart-495af2b5-8544-4ac7-81ef-fc4c1239edc1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719722651 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.2719722651 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_sideload/latest

Test location /workspace/coverage/default/34.kmac_smoke.2352497259
Short name T207
Test name
Test status
Simulation time 6494865599 ps
CPU time 58.23 seconds
Started Jul 25 05:16:43 PM PDT 24
Finished Jul 25 05:17:41 PM PDT 24
Peak memory 218612 kb
Host smart-7be39dd7-45eb-42ca-a296-c198597fd662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352497259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.2352497259 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_smoke/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_kmac.3356193280
Short name T968
Test name
Test status
Simulation time 257393692 ps
CPU time 5.85 seconds
Started Jul 25 05:16:53 PM PDT 24
Finished Jul 25 05:16:59 PM PDT 24
Peak memory 218492 kb
Host smart-4dfdfeb1-1392-4454-8133-e67eec19fcc3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356193280 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.kmac_test_vectors_kmac.3356193280 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_kmac_xof.811801816
Short name T916
Test name
Test status
Simulation time 1100768568 ps
CPU time 6.53 seconds
Started Jul 25 05:16:53 PM PDT 24
Finished Jul 25 05:16:59 PM PDT 24
Peak memory 218596 kb
Host smart-3cda704f-1fc7-4a16-9db8-183f40286960
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811801816 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.kmac_test_vectors_kmac_xof.811801816 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_224.2449969157
Short name T594
Test name
Test status
Simulation time 20401290341 ps
CPU time 1895.81 seconds
Started Jul 25 05:16:45 PM PDT 24
Finished Jul 25 05:48:21 PM PDT 24
Peak memory 397532 kb
Host smart-62970461-6f79-4f04-b734-6f3839ae5dfc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2449969157 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_224.2449969157 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_256.338487902
Short name T914
Test name
Test status
Simulation time 22261914131 ps
CPU time 1862.24 seconds
Started Jul 25 05:16:44 PM PDT 24
Finished Jul 25 05:47:47 PM PDT 24
Peak memory 390408 kb
Host smart-0c223bf2-add2-4131-95d1-7f36e902bc45
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=338487902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_256.338487902 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_384.1423975374
Short name T276
Test name
Test status
Simulation time 61236523377 ps
CPU time 1661.95 seconds
Started Jul 25 05:16:48 PM PDT 24
Finished Jul 25 05:44:30 PM PDT 24
Peak memory 340824 kb
Host smart-c3a6e366-e92d-4aef-9e23-dedcced2bfa7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1423975374 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_384.1423975374 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_512.2313449053
Short name T572
Test name
Test status
Simulation time 68469567894 ps
CPU time 1231.56 seconds
Started Jul 25 05:17:01 PM PDT 24
Finished Jul 25 05:37:33 PM PDT 24
Peak memory 302348 kb
Host smart-8cb300ee-f6e4-42db-b280-f7257b996717
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2313449053 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_512.2313449053 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_shake_128.204569909
Short name T302
Test name
Test status
Simulation time 360034288547 ps
CPU time 5308.23 seconds
Started Jul 25 05:16:52 PM PDT 24
Finished Jul 25 06:45:21 PM PDT 24
Peak memory 664900 kb
Host smart-8f80b711-142a-4d05-bd5e-4ad90499b6c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=204569909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_128.204569909 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_shake_256.772575935
Short name T343
Test name
Test status
Simulation time 150786119967 ps
CPU time 4951.42 seconds
Started Jul 25 05:16:56 PM PDT 24
Finished Jul 25 06:39:29 PM PDT 24
Peak memory 568292 kb
Host smart-c6e51ad6-ee3c-45ca-9d80-61e34b4f0a84
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=772575935 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_256.772575935 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/35.kmac_alert_test.1011121911
Short name T687
Test name
Test status
Simulation time 17680720 ps
CPU time 0.88 seconds
Started Jul 25 05:17:20 PM PDT 24
Finished Jul 25 05:17:21 PM PDT 24
Peak memory 218284 kb
Host smart-4419e749-0ed8-442e-a7ff-bb511574fc55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011121911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.1011121911 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_alert_test/latest

Test location /workspace/coverage/default/35.kmac_app.2569457614
Short name T769
Test name
Test status
Simulation time 19488202108 ps
CPU time 228.76 seconds
Started Jul 25 05:17:12 PM PDT 24
Finished Jul 25 05:21:01 PM PDT 24
Peak memory 246004 kb
Host smart-959283cc-258c-4451-a71a-945c084bef79
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569457614 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.2569457614 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/35.kmac_app/latest

Test location /workspace/coverage/default/35.kmac_burst_write.1845670252
Short name T334
Test name
Test status
Simulation time 105384067142 ps
CPU time 1038.01 seconds
Started Jul 25 05:17:02 PM PDT 24
Finished Jul 25 05:34:20 PM PDT 24
Peak memory 243072 kb
Host smart-f1fb1d9a-f9a6-4283-8d09-47d540946612
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845670252 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.184567025
2 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_burst_write/latest

Test location /workspace/coverage/default/35.kmac_entropy_refresh.3780169869
Short name T1042
Test name
Test status
Simulation time 18309328340 ps
CPU time 168.9 seconds
Started Jul 25 05:17:11 PM PDT 24
Finished Jul 25 05:20:00 PM PDT 24
Peak memory 239272 kb
Host smart-292ddfbc-6236-44df-9bd4-05387a752e40
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780169869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.3
780169869 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/35.kmac_error.132766208
Short name T339
Test name
Test status
Simulation time 3526696889 ps
CPU time 90.28 seconds
Started Jul 25 05:17:10 PM PDT 24
Finished Jul 25 05:18:40 PM PDT 24
Peak memory 243012 kb
Host smart-e8179135-ece8-4826-b252-8fc20752ac67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132766208 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.132766208 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_error/latest

Test location /workspace/coverage/default/35.kmac_key_error.1256612901
Short name T587
Test name
Test status
Simulation time 15446093542 ps
CPU time 15.92 seconds
Started Jul 25 05:17:11 PM PDT 24
Finished Jul 25 05:17:27 PM PDT 24
Peak memory 224904 kb
Host smart-7f3cd434-bcc2-4a38-9c6a-b435f03945cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256612901 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.1256612901 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_key_error/latest

Test location /workspace/coverage/default/35.kmac_lc_escalation.1449075927
Short name T966
Test name
Test status
Simulation time 34815478 ps
CPU time 1.34 seconds
Started Jul 25 05:17:15 PM PDT 24
Finished Jul 25 05:17:17 PM PDT 24
Peak memory 226472 kb
Host smart-9f7d565f-91c3-417d-997a-bf9d907d6ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449075927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.1449075927 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/35.kmac_lc_escalation/latest

Test location /workspace/coverage/default/35.kmac_long_msg_and_output.452470993
Short name T819
Test name
Test status
Simulation time 78078973597 ps
CPU time 1980.4 seconds
Started Jul 25 05:17:01 PM PDT 24
Finished Jul 25 05:50:02 PM PDT 24
Peak memory 376388 kb
Host smart-fc68469b-5288-40c1-80f0-0296f084b80d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452470993 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_an
d_output.452470993 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/35.kmac_sideload.2466759317
Short name T1073
Test name
Test status
Simulation time 222935232 ps
CPU time 18.59 seconds
Started Jul 25 05:17:02 PM PDT 24
Finished Jul 25 05:17:21 PM PDT 24
Peak memory 220304 kb
Host smart-93c9553e-0f52-4a26-8c09-8290b3f691a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466759317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.2466759317 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_sideload/latest

Test location /workspace/coverage/default/35.kmac_smoke.3129433879
Short name T148
Test name
Test status
Simulation time 4562996239 ps
CPU time 91 seconds
Started Jul 25 05:17:04 PM PDT 24
Finished Jul 25 05:18:35 PM PDT 24
Peak memory 226628 kb
Host smart-8cd658ff-58eb-4bb1-9d50-80bf1b7624e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129433879 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.3129433879 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_smoke/latest

Test location /workspace/coverage/default/35.kmac_stress_all.1107640139
Short name T9
Test name
Test status
Simulation time 19944103331 ps
CPU time 127.86 seconds
Started Jul 25 05:17:12 PM PDT 24
Finished Jul 25 05:19:20 PM PDT 24
Peak memory 251140 kb
Host smart-bff26f6c-2dda-492b-b59a-4d5866629a3f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1107640139 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.1107640139 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_stress_all/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_kmac.3419037464
Short name T726
Test name
Test status
Simulation time 110252826 ps
CPU time 6.09 seconds
Started Jul 25 05:17:12 PM PDT 24
Finished Jul 25 05:17:18 PM PDT 24
Peak memory 218628 kb
Host smart-b0a666cf-7f49-4f91-8261-d9c71f56905a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419037464 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.kmac_test_vectors_kmac.3419037464 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_kmac_xof.1886277115
Short name T883
Test name
Test status
Simulation time 1300400453 ps
CPU time 7.18 seconds
Started Jul 25 05:17:16 PM PDT 24
Finished Jul 25 05:17:23 PM PDT 24
Peak memory 219376 kb
Host smart-a6a4bf28-7ce4-4d0a-bba9-2329897813b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886277115 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.kmac_test_vectors_kmac_xof.1886277115 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_224.2139586437
Short name T346
Test name
Test status
Simulation time 172246224407 ps
CPU time 2217.14 seconds
Started Jul 25 05:17:03 PM PDT 24
Finished Jul 25 05:54:01 PM PDT 24
Peak memory 395776 kb
Host smart-716b7238-4486-4ada-93a3-d0c506a62cd6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2139586437 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_224.2139586437 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_256.4045167253
Short name T470
Test name
Test status
Simulation time 380790387056 ps
CPU time 2340.47 seconds
Started Jul 25 05:17:04 PM PDT 24
Finished Jul 25 05:56:04 PM PDT 24
Peak memory 399452 kb
Host smart-a75e1c1b-e6b1-47a3-a181-b3adad89ab92
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4045167253 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_256.4045167253 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_384.3301286844
Short name T271
Test name
Test status
Simulation time 19295525927 ps
CPU time 1528.69 seconds
Started Jul 25 05:17:05 PM PDT 24
Finished Jul 25 05:42:34 PM PDT 24
Peak memory 339596 kb
Host smart-4c94dda3-897d-43dd-bfd7-5269d39031fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3301286844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_384.3301286844 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_512.1210758553
Short name T876
Test name
Test status
Simulation time 488809492187 ps
CPU time 1551.59 seconds
Started Jul 25 05:17:03 PM PDT 24
Finished Jul 25 05:42:54 PM PDT 24
Peak memory 306200 kb
Host smart-f610b2c7-dada-4628-ad99-b12b13c7d52b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1210758553 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_512.1210758553 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_shake_128.527987083
Short name T493
Test name
Test status
Simulation time 528512827442 ps
CPU time 6023.51 seconds
Started Jul 25 05:17:05 PM PDT 24
Finished Jul 25 06:57:29 PM PDT 24
Peak memory 652268 kb
Host smart-71583b04-ccf3-4fcc-8b7c-0a88077c9a62
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=527987083 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_128.527987083 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_shake_256.2219413073
Short name T792
Test name
Test status
Simulation time 184844456633 ps
CPU time 4631.44 seconds
Started Jul 25 05:17:04 PM PDT 24
Finished Jul 25 06:34:16 PM PDT 24
Peak memory 573184 kb
Host smart-d0c56a6e-12b5-43ed-9e87-11f45fbe5827
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2219413073 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_256.2219413073 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/36.kmac_alert_test.1714183391
Short name T293
Test name
Test status
Simulation time 17286217 ps
CPU time 0.88 seconds
Started Jul 25 05:17:37 PM PDT 24
Finished Jul 25 05:17:38 PM PDT 24
Peak memory 218260 kb
Host smart-a20928bc-58bd-4bb7-9570-e8d8fb9e8b65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714183391 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.1714183391 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_alert_test/latest

Test location /workspace/coverage/default/36.kmac_app.123231304
Short name T495
Test name
Test status
Simulation time 2957398967 ps
CPU time 174.86 seconds
Started Jul 25 05:17:28 PM PDT 24
Finished Jul 25 05:20:23 PM PDT 24
Peak memory 241600 kb
Host smart-1fb66c3e-e670-401a-b385-d6c7f93b678b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123231304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.123231304 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/36.kmac_app/latest

Test location /workspace/coverage/default/36.kmac_burst_write.2664576235
Short name T857
Test name
Test status
Simulation time 37852289163 ps
CPU time 372.22 seconds
Started Jul 25 05:17:22 PM PDT 24
Finished Jul 25 05:23:34 PM PDT 24
Peak memory 230732 kb
Host smart-801c879e-95c0-4139-9b60-808e610b6e8e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664576235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.266457623
5 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_burst_write/latest

Test location /workspace/coverage/default/36.kmac_entropy_refresh.4006230502
Short name T975
Test name
Test status
Simulation time 6362592476 ps
CPU time 113.59 seconds
Started Jul 25 05:17:32 PM PDT 24
Finished Jul 25 05:19:26 PM PDT 24
Peak memory 234604 kb
Host smart-027ef117-caff-4e48-8233-2e006f4b91fe
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006230502 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.4
006230502 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/36.kmac_error.4047029573
Short name T694
Test name
Test status
Simulation time 1264047342 ps
CPU time 101.22 seconds
Started Jul 25 05:17:27 PM PDT 24
Finished Jul 25 05:19:09 PM PDT 24
Peak memory 242956 kb
Host smart-b819463e-cea2-48ab-804c-9167fad3c7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047029573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.4047029573 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_error/latest

Test location /workspace/coverage/default/36.kmac_key_error.1278760319
Short name T261
Test name
Test status
Simulation time 4909370664 ps
CPU time 9.12 seconds
Started Jul 25 05:17:28 PM PDT 24
Finished Jul 25 05:17:37 PM PDT 24
Peak memory 224064 kb
Host smart-1c7f431e-9f77-4b1a-9664-e3fddd9b51c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278760319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.1278760319 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_key_error/latest

Test location /workspace/coverage/default/36.kmac_lc_escalation.1367884948
Short name T116
Test name
Test status
Simulation time 43138642 ps
CPU time 1.3 seconds
Started Jul 25 05:17:29 PM PDT 24
Finished Jul 25 05:17:30 PM PDT 24
Peak memory 226608 kb
Host smart-0a11ae91-63b1-44a7-8b59-983f23e3413d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367884948 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.1367884948 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/36.kmac_lc_escalation/latest

Test location /workspace/coverage/default/36.kmac_long_msg_and_output.2473250688
Short name T447
Test name
Test status
Simulation time 18749274399 ps
CPU time 555.44 seconds
Started Jul 25 05:17:22 PM PDT 24
Finished Jul 25 05:26:38 PM PDT 24
Peak memory 264076 kb
Host smart-015e96d1-5500-40c5-9484-02495c753e77
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473250688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_a
nd_output.2473250688 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/36.kmac_sideload.2550913123
Short name T630
Test name
Test status
Simulation time 4368506416 ps
CPU time 385.69 seconds
Started Jul 25 05:17:19 PM PDT 24
Finished Jul 25 05:23:45 PM PDT 24
Peak memory 248468 kb
Host smart-9161b1aa-9a58-4393-a4f4-de0f01af8d28
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550913123 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.2550913123 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_sideload/latest

Test location /workspace/coverage/default/36.kmac_smoke.3448178019
Short name T965
Test name
Test status
Simulation time 2671574118 ps
CPU time 63.52 seconds
Started Jul 25 05:17:20 PM PDT 24
Finished Jul 25 05:18:24 PM PDT 24
Peak memory 223108 kb
Host smart-3c29946d-b3af-4a5d-8faa-2fdd5432f3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448178019 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.3448178019 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_smoke/latest

Test location /workspace/coverage/default/36.kmac_stress_all.2455224144
Short name T1025
Test name
Test status
Simulation time 35083723708 ps
CPU time 1145.91 seconds
Started Jul 25 05:17:35 PM PDT 24
Finished Jul 25 05:36:42 PM PDT 24
Peak memory 356352 kb
Host smart-8e4923c7-a09c-4472-ace6-6cb46a7b3ca1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2455224144 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.2455224144 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_stress_all/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_kmac.1040479987
Short name T862
Test name
Test status
Simulation time 113673809 ps
CPU time 5.91 seconds
Started Jul 25 05:17:28 PM PDT 24
Finished Jul 25 05:17:34 PM PDT 24
Peak memory 219440 kb
Host smart-ce0dfb71-5fe7-4e26-b3e1-36fe764625c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040479987 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.kmac_test_vectors_kmac.1040479987 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_kmac_xof.1325034832
Short name T745
Test name
Test status
Simulation time 382969651 ps
CPU time 6.24 seconds
Started Jul 25 05:17:25 PM PDT 24
Finished Jul 25 05:17:32 PM PDT 24
Peak memory 218476 kb
Host smart-343f6dda-8142-4341-b3f5-6946748f4a54
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325034832 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.kmac_test_vectors_kmac_xof.1325034832 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_224.2708455035
Short name T476
Test name
Test status
Simulation time 398905539358 ps
CPU time 2432.11 seconds
Started Jul 25 05:17:21 PM PDT 24
Finished Jul 25 05:57:53 PM PDT 24
Peak memory 390380 kb
Host smart-19de76ae-d591-452a-af58-8188a434f04d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2708455035 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_224.2708455035 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_256.2396067714
Short name T984
Test name
Test status
Simulation time 39915787385 ps
CPU time 1898.7 seconds
Started Jul 25 05:17:20 PM PDT 24
Finished Jul 25 05:48:59 PM PDT 24
Peak memory 384656 kb
Host smart-00704b3b-a01a-4a5f-9a14-26f22a7d0a13
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2396067714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_256.2396067714 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_384.1966147750
Short name T294
Test name
Test status
Simulation time 74003632827 ps
CPU time 1888.94 seconds
Started Jul 25 05:17:18 PM PDT 24
Finished Jul 25 05:48:47 PM PDT 24
Peak memory 337372 kb
Host smart-cf7c27eb-d429-46c9-ad7b-2a30f7368faf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1966147750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_384.1966147750 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_512.1572702444
Short name T253
Test name
Test status
Simulation time 139502131610 ps
CPU time 1249.62 seconds
Started Jul 25 05:17:22 PM PDT 24
Finished Jul 25 05:38:11 PM PDT 24
Peak memory 298900 kb
Host smart-efd6338a-cba5-46a3-a3e8-b87ee68bc754
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1572702444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_512.1572702444 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_shake_128.834675774
Short name T676
Test name
Test status
Simulation time 82661576241 ps
CPU time 5172.95 seconds
Started Jul 25 05:17:31 PM PDT 24
Finished Jul 25 06:43:44 PM PDT 24
Peak memory 656656 kb
Host smart-3747fe89-3d10-44ca-b00c-f72ed8c61148
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=834675774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_128.834675774 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_shake_256.4076133549
Short name T378
Test name
Test status
Simulation time 166091990055 ps
CPU time 4532.62 seconds
Started Jul 25 05:17:29 PM PDT 24
Finished Jul 25 06:33:02 PM PDT 24
Peak memory 566692 kb
Host smart-db406f93-09c0-46ce-af0b-a1a5b71f3745
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4076133549 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_256.4076133549 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/37.kmac_alert_test.2760165682
Short name T873
Test name
Test status
Simulation time 21496074 ps
CPU time 0.85 seconds
Started Jul 25 05:17:54 PM PDT 24
Finished Jul 25 05:17:55 PM PDT 24
Peak memory 218236 kb
Host smart-ce4d49fc-8534-40aa-b376-8f75e2067023
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760165682 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.2760165682 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_alert_test/latest

Test location /workspace/coverage/default/37.kmac_app.1558357829
Short name T98
Test name
Test status
Simulation time 73535992476 ps
CPU time 375.19 seconds
Started Jul 25 05:17:46 PM PDT 24
Finished Jul 25 05:24:01 PM PDT 24
Peak memory 251024 kb
Host smart-5fbd50e5-b1f1-4c27-a554-b9f62be5a22d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558357829 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.1558357829 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/37.kmac_app/latest

Test location /workspace/coverage/default/37.kmac_burst_write.541070411
Short name T655
Test name
Test status
Simulation time 26020925207 ps
CPU time 867.2 seconds
Started Jul 25 05:17:38 PM PDT 24
Finished Jul 25 05:32:05 PM PDT 24
Peak memory 236808 kb
Host smart-790b4c92-5bba-4c20-b85b-474cf1e6e112
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541070411 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.541070411
+enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_burst_write/latest

Test location /workspace/coverage/default/37.kmac_entropy_refresh.523930722
Short name T429
Test name
Test status
Simulation time 228649869 ps
CPU time 5.12 seconds
Started Jul 25 05:17:45 PM PDT 24
Finished Jul 25 05:17:50 PM PDT 24
Peak memory 222732 kb
Host smart-c181091f-313f-4cd9-ba25-baef0e3bc14b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523930722 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.52
3930722 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/37.kmac_error.278840533
Short name T812
Test name
Test status
Simulation time 5111843884 ps
CPU time 406.14 seconds
Started Jul 25 05:17:45 PM PDT 24
Finished Jul 25 05:24:32 PM PDT 24
Peak memory 259428 kb
Host smart-5ed9b52f-281e-4151-936e-44757a876833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278840533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.278840533 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_error/latest

Test location /workspace/coverage/default/37.kmac_key_error.816551396
Short name T803
Test name
Test status
Simulation time 526089905 ps
CPU time 2.11 seconds
Started Jul 25 05:17:54 PM PDT 24
Finished Jul 25 05:17:56 PM PDT 24
Peak memory 222520 kb
Host smart-88b592b4-b646-42fd-b19a-cf2ce332eb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816551396 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.816551396 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_key_error/latest

Test location /workspace/coverage/default/37.kmac_lc_escalation.2471641864
Short name T356
Test name
Test status
Simulation time 48727248 ps
CPU time 1.21 seconds
Started Jul 25 05:17:53 PM PDT 24
Finished Jul 25 05:17:54 PM PDT 24
Peak memory 226572 kb
Host smart-534a5047-d628-439c-b8d3-a85c25728bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471641864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.2471641864 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/37.kmac_lc_escalation/latest

Test location /workspace/coverage/default/37.kmac_long_msg_and_output.410813737
Short name T685
Test name
Test status
Simulation time 199956299680 ps
CPU time 2119.63 seconds
Started Jul 25 05:17:39 PM PDT 24
Finished Jul 25 05:52:59 PM PDT 24
Peak memory 390704 kb
Host smart-508d530b-ce95-45a1-beea-982d404dd7eb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410813737 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_an
d_output.410813737 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/37.kmac_sideload.3143135253
Short name T908
Test name
Test status
Simulation time 12637004623 ps
CPU time 365.02 seconds
Started Jul 25 05:17:38 PM PDT 24
Finished Jul 25 05:23:43 PM PDT 24
Peak memory 250628 kb
Host smart-08a68181-7333-4e39-b6a1-f941f00d7674
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143135253 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.3143135253 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_sideload/latest

Test location /workspace/coverage/default/37.kmac_smoke.1687087566
Short name T479
Test name
Test status
Simulation time 3091521334 ps
CPU time 64.59 seconds
Started Jul 25 05:17:39 PM PDT 24
Finished Jul 25 05:18:43 PM PDT 24
Peak memory 223144 kb
Host smart-bbe8c5a8-2008-4ee8-bfa0-4d3352ffec70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687087566 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.1687087566 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_smoke/latest

Test location /workspace/coverage/default/37.kmac_stress_all.2935020211
Short name T798
Test name
Test status
Simulation time 187342969914 ps
CPU time 2491.82 seconds
Started Jul 25 05:17:53 PM PDT 24
Finished Jul 25 05:59:25 PM PDT 24
Peak memory 450916 kb
Host smart-090d4886-233b-4160-a601-3baab0b475ff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2935020211 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.2935020211 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_stress_all/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_kmac.1926361847
Short name T539
Test name
Test status
Simulation time 527589731 ps
CPU time 6.53 seconds
Started Jul 25 05:17:46 PM PDT 24
Finished Jul 25 05:17:53 PM PDT 24
Peak memory 218600 kb
Host smart-eca30e9c-d376-44d8-afad-226711113ffb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926361847 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.kmac_test_vectors_kmac.1926361847 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_kmac_xof.56620961
Short name T588
Test name
Test status
Simulation time 439470462 ps
CPU time 5.87 seconds
Started Jul 25 05:17:51 PM PDT 24
Finished Jul 25 05:17:57 PM PDT 24
Peak memory 218616 kb
Host smart-9a373804-4949-468f-acac-bbbc495be395
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56620961 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.kmac_test_vectors_kmac_xof.56620961 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_224.2606598856
Short name T200
Test name
Test status
Simulation time 340727239416 ps
CPU time 2332.47 seconds
Started Jul 25 05:17:49 PM PDT 24
Finished Jul 25 05:56:42 PM PDT 24
Peak memory 399836 kb
Host smart-18270666-91f4-499b-b7ba-65383000162d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2606598856 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_224.2606598856 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_256.2573412667
Short name T1066
Test name
Test status
Simulation time 88128451372 ps
CPU time 1874.84 seconds
Started Jul 25 05:17:46 PM PDT 24
Finished Jul 25 05:49:01 PM PDT 24
Peak memory 390488 kb
Host smart-e41dcfaf-8ba8-4817-83a3-1bdc49a4c46c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2573412667 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_256.2573412667 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_384.3391648339
Short name T248
Test name
Test status
Simulation time 29568029618 ps
CPU time 1455.46 seconds
Started Jul 25 05:17:45 PM PDT 24
Finished Jul 25 05:42:00 PM PDT 24
Peak memory 335064 kb
Host smart-1b572245-7869-454e-8777-b3ce24963557
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3391648339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_384.3391648339 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_512.1708143313
Short name T775
Test name
Test status
Simulation time 359698470951 ps
CPU time 1414.01 seconds
Started Jul 25 05:17:43 PM PDT 24
Finished Jul 25 05:41:17 PM PDT 24
Peak memory 304476 kb
Host smart-44c7c479-7e0e-4db0-8fda-3a1a4539eb3c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1708143313 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_512.1708143313 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_shake_128.2898918304
Short name T659
Test name
Test status
Simulation time 59971117554 ps
CPU time 4772.18 seconds
Started Jul 25 05:17:51 PM PDT 24
Finished Jul 25 06:37:24 PM PDT 24
Peak memory 655484 kb
Host smart-7f9ae7d1-59c2-4e6c-9464-287931fe3e97
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2898918304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_128.2898918304 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_shake_256.3006099526
Short name T863
Test name
Test status
Simulation time 945854854392 ps
CPU time 4913.4 seconds
Started Jul 25 05:17:53 PM PDT 24
Finished Jul 25 06:39:47 PM PDT 24
Peak memory 562608 kb
Host smart-4b6b9a80-d921-43a9-a2fb-21de81e290ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3006099526 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_256.3006099526 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/38.kmac_alert_test.3649799597
Short name T766
Test name
Test status
Simulation time 16310594 ps
CPU time 0.81 seconds
Started Jul 25 05:18:09 PM PDT 24
Finished Jul 25 05:18:10 PM PDT 24
Peak memory 218252 kb
Host smart-93c372bc-d233-4a11-9420-610ea89344c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649799597 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.3649799597 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_alert_test/latest

Test location /workspace/coverage/default/38.kmac_app.864044241
Short name T1063
Test name
Test status
Simulation time 9893698575 ps
CPU time 319.54 seconds
Started Jul 25 05:18:02 PM PDT 24
Finished Jul 25 05:23:22 PM PDT 24
Peak memory 249168 kb
Host smart-3b8021ce-ac92-4d33-8818-154b750bb80b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864044241 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.864044241 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/38.kmac_app/latest

Test location /workspace/coverage/default/38.kmac_burst_write.1729898321
Short name T519
Test name
Test status
Simulation time 60935116399 ps
CPU time 818.8 seconds
Started Jul 25 05:18:03 PM PDT 24
Finished Jul 25 05:31:42 PM PDT 24
Peak memory 236952 kb
Host smart-f116c54a-4478-45d8-92b4-1de8a91beabb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729898321 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.172989832
1 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_burst_write/latest

Test location /workspace/coverage/default/38.kmac_entropy_refresh.3063765079
Short name T257
Test name
Test status
Simulation time 45102565038 ps
CPU time 296.35 seconds
Started Jul 25 05:18:03 PM PDT 24
Finished Jul 25 05:22:59 PM PDT 24
Peak memory 248948 kb
Host smart-03209526-13c1-4feb-b519-f2532701919f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063765079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.3
063765079 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/38.kmac_error.229167428
Short name T23
Test name
Test status
Simulation time 55901381253 ps
CPU time 485.55 seconds
Started Jul 25 05:18:03 PM PDT 24
Finished Jul 25 05:26:09 PM PDT 24
Peak memory 259368 kb
Host smart-c3ff99ba-cebc-4190-984c-805b35036d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229167428 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.229167428 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_error/latest

Test location /workspace/coverage/default/38.kmac_key_error.2870649680
Short name T540
Test name
Test status
Simulation time 3140803547 ps
CPU time 11.07 seconds
Started Jul 25 05:18:04 PM PDT 24
Finished Jul 25 05:18:15 PM PDT 24
Peak memory 218456 kb
Host smart-838e7b06-6afa-427d-9ca9-791d9fb7292a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870649680 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.2870649680 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_key_error/latest

Test location /workspace/coverage/default/38.kmac_lc_escalation.589261748
Short name T874
Test name
Test status
Simulation time 261397939 ps
CPU time 5.24 seconds
Started Jul 25 05:18:06 PM PDT 24
Finished Jul 25 05:18:11 PM PDT 24
Peak memory 226684 kb
Host smart-77ecd0de-4e10-4d7b-96f0-757854bfe286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589261748 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.589261748 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/38.kmac_lc_escalation/latest

Test location /workspace/coverage/default/38.kmac_long_msg_and_output.1147870989
Short name T858
Test name
Test status
Simulation time 121188985997 ps
CPU time 3088.85 seconds
Started Jul 25 05:17:53 PM PDT 24
Finished Jul 25 06:09:23 PM PDT 24
Peak memory 464272 kb
Host smart-2ee3ae3e-d6da-4bbf-bd10-eb6afd09e5f1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147870989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_a
nd_output.1147870989 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/38.kmac_sideload.323771269
Short name T269
Test name
Test status
Simulation time 8171711277 ps
CPU time 451.77 seconds
Started Jul 25 05:17:52 PM PDT 24
Finished Jul 25 05:25:24 PM PDT 24
Peak memory 255156 kb
Host smart-046d36c1-f3dd-42f1-8ad6-769cf743ff53
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323771269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.323771269 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_sideload/latest

Test location /workspace/coverage/default/38.kmac_smoke.461676878
Short name T299
Test name
Test status
Simulation time 1803941674 ps
CPU time 72.61 seconds
Started Jul 25 05:17:50 PM PDT 24
Finished Jul 25 05:19:03 PM PDT 24
Peak memory 222760 kb
Host smart-1b09a95a-8e5f-4a46-b5b5-8c75bd17f848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461676878 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.461676878 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_smoke/latest

Test location /workspace/coverage/default/38.kmac_stress_all.3682845548
Short name T921
Test name
Test status
Simulation time 3923109382 ps
CPU time 91.48 seconds
Started Jul 25 05:18:02 PM PDT 24
Finished Jul 25 05:19:34 PM PDT 24
Peak memory 242272 kb
Host smart-a9203bb3-3ca6-4bf0-96b4-04fe2890f99d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3682845548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.3682845548 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_stress_all/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_kmac.1805394438
Short name T570
Test name
Test status
Simulation time 149724725 ps
CPU time 5.72 seconds
Started Jul 25 05:18:03 PM PDT 24
Finished Jul 25 05:18:09 PM PDT 24
Peak memory 218604 kb
Host smart-062c70ce-da32-4fa4-9c02-2a1e1add255e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805394438 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.kmac_test_vectors_kmac.1805394438 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_kmac_xof.1736547839
Short name T706
Test name
Test status
Simulation time 109296409 ps
CPU time 5.56 seconds
Started Jul 25 05:18:04 PM PDT 24
Finished Jul 25 05:18:10 PM PDT 24
Peak memory 219468 kb
Host smart-d46aadaf-4c70-4a6c-b5be-5d78146df86d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736547839 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.kmac_test_vectors_kmac_xof.1736547839 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_224.794237698
Short name T755
Test name
Test status
Simulation time 85060057956 ps
CPU time 2038.75 seconds
Started Jul 25 05:18:06 PM PDT 24
Finished Jul 25 05:52:05 PM PDT 24
Peak memory 395904 kb
Host smart-178002d2-8097-4f4c-b938-246f5bce8b49
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=794237698 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_224.794237698 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_256.1474516504
Short name T865
Test name
Test status
Simulation time 92882162507 ps
CPU time 2253.48 seconds
Started Jul 25 05:18:01 PM PDT 24
Finished Jul 25 05:55:34 PM PDT 24
Peak memory 387600 kb
Host smart-65f79ec7-7f2b-433d-832b-ccb37a790cec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1474516504 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_256.1474516504 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_384.1738706490
Short name T413
Test name
Test status
Simulation time 99010061840 ps
CPU time 1675.39 seconds
Started Jul 25 05:18:08 PM PDT 24
Finished Jul 25 05:46:03 PM PDT 24
Peak memory 340104 kb
Host smart-3a19363e-8192-4f81-b5d0-52814ad5435a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1738706490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_384.1738706490 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_512.127234369
Short name T722
Test name
Test status
Simulation time 71154636134 ps
CPU time 1165.07 seconds
Started Jul 25 05:18:01 PM PDT 24
Finished Jul 25 05:37:26 PM PDT 24
Peak memory 297468 kb
Host smart-d346b056-56d1-45a5-bef2-23ee20f5c1ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=127234369 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_512.127234369 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_shake_128.21017232
Short name T849
Test name
Test status
Simulation time 1268020278190 ps
CPU time 6158.96 seconds
Started Jul 25 05:18:03 PM PDT 24
Finished Jul 25 07:00:43 PM PDT 24
Peak memory 662616 kb
Host smart-3d59f9ba-2c45-4f24-870b-d5b45817a940
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=21017232 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_128.21017232 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_shake_256.3201870511
Short name T481
Test name
Test status
Simulation time 718805160522 ps
CPU time 4967.68 seconds
Started Jul 25 05:18:02 PM PDT 24
Finished Jul 25 06:40:50 PM PDT 24
Peak memory 571648 kb
Host smart-32e6a4e6-e4e7-4ba4-b45b-3676827abe96
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3201870511 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_256.3201870511 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/39.kmac_alert_test.1794143482
Short name T805
Test name
Test status
Simulation time 20729200 ps
CPU time 0.89 seconds
Started Jul 25 05:18:23 PM PDT 24
Finished Jul 25 05:18:24 PM PDT 24
Peak memory 218280 kb
Host smart-a1fe42fc-b337-4ca2-ae2d-4eed595a1719
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794143482 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.1794143482 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_alert_test/latest

Test location /workspace/coverage/default/39.kmac_app.3333338436
Short name T511
Test name
Test status
Simulation time 9592134184 ps
CPU time 52.61 seconds
Started Jul 25 05:18:45 PM PDT 24
Finished Jul 25 05:19:38 PM PDT 24
Peak memory 226904 kb
Host smart-d4b0efa0-5f6f-499b-9f24-f97b3cfe358b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333338436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.3333338436 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/39.kmac_app/latest

Test location /workspace/coverage/default/39.kmac_burst_write.954233400
Short name T380
Test name
Test status
Simulation time 152813081479 ps
CPU time 1699.11 seconds
Started Jul 25 05:18:12 PM PDT 24
Finished Jul 25 05:46:32 PM PDT 24
Peak memory 238988 kb
Host smart-76f50c65-7a24-4d86-9339-87f519a5013c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954233400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.954233400
+enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_burst_write/latest

Test location /workspace/coverage/default/39.kmac_entropy_refresh.1190660233
Short name T496
Test name
Test status
Simulation time 46890166636 ps
CPU time 296.13 seconds
Started Jul 25 05:18:22 PM PDT 24
Finished Jul 25 05:23:18 PM PDT 24
Peak memory 246252 kb
Host smart-479fdf12-45c5-4aa8-bee9-17f6dc99da81
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190660233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.1
190660233 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/39.kmac_error.377726656
Short name T1050
Test name
Test status
Simulation time 6881827821 ps
CPU time 43.44 seconds
Started Jul 25 05:18:18 PM PDT 24
Finished Jul 25 05:19:01 PM PDT 24
Peak memory 236388 kb
Host smart-7ed98b30-92a1-4b16-88be-54af29269f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377726656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.377726656 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_error/latest

Test location /workspace/coverage/default/39.kmac_key_error.3024993062
Short name T42
Test name
Test status
Simulation time 3291730354 ps
CPU time 11.96 seconds
Started Jul 25 05:18:22 PM PDT 24
Finished Jul 25 05:18:34 PM PDT 24
Peak memory 225484 kb
Host smart-efdd552d-2780-41d1-85f7-dfdd4549ccfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024993062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.3024993062 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_key_error/latest

Test location /workspace/coverage/default/39.kmac_lc_escalation.735836116
Short name T1044
Test name
Test status
Simulation time 64883127 ps
CPU time 1.24 seconds
Started Jul 25 05:18:20 PM PDT 24
Finished Jul 25 05:18:21 PM PDT 24
Peak memory 226592 kb
Host smart-69f18956-b803-49ce-b6f4-cc3d358f89da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735836116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.735836116 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/39.kmac_lc_escalation/latest

Test location /workspace/coverage/default/39.kmac_long_msg_and_output.1133695128
Short name T272
Test name
Test status
Simulation time 47987674749 ps
CPU time 2550.91 seconds
Started Jul 25 05:18:19 PM PDT 24
Finished Jul 25 06:00:50 PM PDT 24
Peak memory 449260 kb
Host smart-b8f480e2-ec58-4b1e-a432-c82456f92fb7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133695128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_a
nd_output.1133695128 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/39.kmac_sideload.28426929
Short name T21
Test name
Test status
Simulation time 7420789641 ps
CPU time 115.64 seconds
Started Jul 25 05:18:11 PM PDT 24
Finished Jul 25 05:20:07 PM PDT 24
Peak memory 231312 kb
Host smart-a3143e61-b0d1-4af5-a5da-b9dbcd472e1b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28426929 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.28426929 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_sideload/latest

Test location /workspace/coverage/default/39.kmac_smoke.2926281183
Short name T633
Test name
Test status
Simulation time 2178003509 ps
CPU time 50.98 seconds
Started Jul 25 05:18:10 PM PDT 24
Finished Jul 25 05:19:01 PM PDT 24
Peak memory 222720 kb
Host smart-242db468-1ead-46d4-ba88-0aa244afcd2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926281183 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.2926281183 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_smoke/latest

Test location /workspace/coverage/default/39.kmac_stress_all.130257009
Short name T599
Test name
Test status
Simulation time 7699314179 ps
CPU time 274.57 seconds
Started Jul 25 05:18:20 PM PDT 24
Finished Jul 25 05:22:54 PM PDT 24
Peak memory 266788 kb
Host smart-73ca69a1-80c8-4710-a70a-bf9a97d48499
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=130257009 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.130257009 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_stress_all/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_kmac.4248061493
Short name T250
Test name
Test status
Simulation time 601234550 ps
CPU time 6.81 seconds
Started Jul 25 05:18:10 PM PDT 24
Finished Jul 25 05:18:16 PM PDT 24
Peak memory 218600 kb
Host smart-65dd3c30-adcf-49e4-a690-f0eecba31efb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248061493 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.kmac_test_vectors_kmac.4248061493 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_kmac_xof.2688683005
Short name T864
Test name
Test status
Simulation time 121896752 ps
CPU time 4.99 seconds
Started Jul 25 05:18:37 PM PDT 24
Finished Jul 25 05:18:42 PM PDT 24
Peak memory 218576 kb
Host smart-d5482946-fbd7-4fc0-b0ed-2d540b21c7c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688683005 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.kmac_test_vectors_kmac_xof.2688683005 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_224.2156008769
Short name T556
Test name
Test status
Simulation time 65804054072 ps
CPU time 2142.07 seconds
Started Jul 25 05:18:11 PM PDT 24
Finished Jul 25 05:53:53 PM PDT 24
Peak memory 398944 kb
Host smart-960b9796-ca4a-43bd-b85b-a167c62945fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2156008769 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_224.2156008769 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_256.109875030
Short name T226
Test name
Test status
Simulation time 19767034432 ps
CPU time 1722.63 seconds
Started Jul 25 05:18:11 PM PDT 24
Finished Jul 25 05:46:54 PM PDT 24
Peak memory 383792 kb
Host smart-4b1aa066-c3a3-4b75-9dd4-8579402dc31c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=109875030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_256.109875030 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_384.2522093405
Short name T1013
Test name
Test status
Simulation time 187337412674 ps
CPU time 1824.98 seconds
Started Jul 25 05:18:11 PM PDT 24
Finished Jul 25 05:48:36 PM PDT 24
Peak memory 336532 kb
Host smart-0c9a8207-92f0-4d2f-b01a-78dacfcea16c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2522093405 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_384.2522093405 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_512.329963507
Short name T546
Test name
Test status
Simulation time 41992685587 ps
CPU time 1188.68 seconds
Started Jul 25 05:18:12 PM PDT 24
Finished Jul 25 05:38:01 PM PDT 24
Peak memory 298060 kb
Host smart-d4a26325-184b-42ff-afd4-fe375742c0c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=329963507 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_512.329963507 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_shake_128.1109031697
Short name T1000
Test name
Test status
Simulation time 735796820650 ps
CPU time 5855 seconds
Started Jul 25 05:18:12 PM PDT 24
Finished Jul 25 06:55:48 PM PDT 24
Peak memory 649256 kb
Host smart-e38671b6-4d90-4f9d-9787-afe67bcc0bdc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1109031697 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_128.1109031697 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_shake_256.1623322403
Short name T149
Test name
Test status
Simulation time 55239043375 ps
CPU time 4446.84 seconds
Started Jul 25 05:18:11 PM PDT 24
Finished Jul 25 06:32:18 PM PDT 24
Peak memory 578044 kb
Host smart-34a420b7-8d33-45cb-80fb-4aaa14beca27
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1623322403 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_256.1623322403 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/4.kmac_alert_test.1642392579
Short name T463
Test name
Test status
Simulation time 13515721 ps
CPU time 0.79 seconds
Started Jul 25 05:12:28 PM PDT 24
Finished Jul 25 05:12:29 PM PDT 24
Peak memory 218292 kb
Host smart-84599fb5-7ce7-44bb-bcef-d570ec4c47b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642392579 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.1642392579 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_alert_test/latest

Test location /workspace/coverage/default/4.kmac_app.617961407
Short name T657
Test name
Test status
Simulation time 6935944891 ps
CPU time 111.62 seconds
Started Jul 25 05:12:25 PM PDT 24
Finished Jul 25 05:14:17 PM PDT 24
Peak memory 235668 kb
Host smart-a57339d7-1263-4b23-bd6a-4f7c3e48329f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617961407 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.617961407 +enable_masking=1
+sw_key_masked=0
Directory /workspace/4.kmac_app/latest

Test location /workspace/coverage/default/4.kmac_app_with_partial_data.526212513
Short name T892
Test name
Test status
Simulation time 15727807481 ps
CPU time 390.04 seconds
Started Jul 25 05:12:24 PM PDT 24
Finished Jul 25 05:18:55 PM PDT 24
Peak memory 253940 kb
Host smart-a4c6675e-5d0c-4264-a228-e62c95f205f2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526212513 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_parti
al_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_part
ial_data.526212513 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/4.kmac_burst_write.3611790928
Short name T456
Test name
Test status
Simulation time 32172415660 ps
CPU time 585.64 seconds
Started Jul 25 05:12:26 PM PDT 24
Finished Jul 25 05:22:12 PM PDT 24
Peak memory 232836 kb
Host smart-beae169d-0194-4628-b092-2c581458d81d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611790928 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.3611790928
+enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_burst_write/latest

Test location /workspace/coverage/default/4.kmac_edn_timeout_error.1176075114
Short name T604
Test name
Test status
Simulation time 2899897390 ps
CPU time 44.08 seconds
Started Jul 25 05:12:28 PM PDT 24
Finished Jul 25 05:13:12 PM PDT 24
Peak memory 228700 kb
Host smart-cf3b3f84-7e61-4708-b45f-f07f1569c470
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1176075114 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.1176075114 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_mode_error.2344525354
Short name T360
Test name
Test status
Simulation time 78254826 ps
CPU time 0.98 seconds
Started Jul 25 05:12:27 PM PDT 24
Finished Jul 25 05:12:28 PM PDT 24
Peak memory 220448 kb
Host smart-6d961fd9-b5c5-45b9-885c-7732cd3f9e2a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2344525354 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.2344525354 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_ready_error.2476194075
Short name T765
Test name
Test status
Simulation time 25026183516 ps
CPU time 83.18 seconds
Started Jul 25 05:12:23 PM PDT 24
Finished Jul 25 05:13:47 PM PDT 24
Peak memory 220980 kb
Host smart-54e92940-ddc1-4b50-9b04-f9327f83334b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476194075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.2476194075 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_refresh.314565921
Short name T548
Test name
Test status
Simulation time 7362097305 ps
CPU time 421.37 seconds
Started Jul 25 05:12:25 PM PDT 24
Finished Jul 25 05:19:27 PM PDT 24
Peak memory 251944 kb
Host smart-14ee64d7-6b86-445e-ae61-ff38f8dc812b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314565921 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.314
565921 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/4.kmac_error.148772976
Short name T24
Test name
Test status
Simulation time 53736797673 ps
CPU time 320.8 seconds
Started Jul 25 05:17:25 PM PDT 24
Finished Jul 25 05:22:46 PM PDT 24
Peak memory 255932 kb
Host smart-9aa95075-6cc4-4537-a7ec-b0ef3c3e5e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148772976 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.148772976 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_error/latest

Test location /workspace/coverage/default/4.kmac_key_error.2176456034
Short name T913
Test name
Test status
Simulation time 509205066 ps
CPU time 4.23 seconds
Started Jul 25 05:12:26 PM PDT 24
Finished Jul 25 05:12:30 PM PDT 24
Peak memory 222568 kb
Host smart-62b66b44-3c9c-4d75-a70f-d946171d6ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176456034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.2176456034 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_key_error/latest

Test location /workspace/coverage/default/4.kmac_lc_escalation.1001038293
Short name T550
Test name
Test status
Simulation time 65469852 ps
CPU time 1.45 seconds
Started Jul 25 05:12:27 PM PDT 24
Finished Jul 25 05:12:28 PM PDT 24
Peak memory 226644 kb
Host smart-b678e790-426d-49cc-8427-66e508ac5c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001038293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.1001038293 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/4.kmac_lc_escalation/latest

Test location /workspace/coverage/default/4.kmac_long_msg_and_output.3428514783
Short name T491
Test name
Test status
Simulation time 49883105926 ps
CPU time 2412.72 seconds
Started Jul 25 05:12:24 PM PDT 24
Finished Jul 25 05:52:38 PM PDT 24
Peak memory 431672 kb
Host smart-32c1a769-7d13-4ff8-98e2-73905f038453
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428514783 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_an
d_output.3428514783 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/4.kmac_mubi.3051870895
Short name T328
Test name
Test status
Simulation time 39485489271 ps
CPU time 307.77 seconds
Started Jul 25 05:12:37 PM PDT 24
Finished Jul 25 05:17:45 PM PDT 24
Peak memory 249388 kb
Host smart-6aa635e7-6dd7-498e-b12f-0caeb4e71c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051870895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.3051870895 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_mubi/latest

Test location /workspace/coverage/default/4.kmac_sec_cm.265321450
Short name T120
Test name
Test status
Simulation time 9782905240 ps
CPU time 88.62 seconds
Started Jul 25 05:12:26 PM PDT 24
Finished Jul 25 05:13:55 PM PDT 24
Peak memory 273956 kb
Host smart-72b66d51-b6cb-4e56-a09b-544a3b98047b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265321450 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.265321450 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/4.kmac_sec_cm/latest

Test location /workspace/coverage/default/4.kmac_sideload.391497891
Short name T583
Test name
Test status
Simulation time 106167985532 ps
CPU time 395.39 seconds
Started Jul 25 05:12:31 PM PDT 24
Finished Jul 25 05:19:06 PM PDT 24
Peak memory 250016 kb
Host smart-ce356b35-55e8-4d24-924d-937fc072ab90
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391497891 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.391497891 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_sideload/latest

Test location /workspace/coverage/default/4.kmac_smoke.3303371718
Short name T761
Test name
Test status
Simulation time 7937809292 ps
CPU time 95.92 seconds
Started Jul 25 05:12:24 PM PDT 24
Finished Jul 25 05:14:00 PM PDT 24
Peak memory 222668 kb
Host smart-7b2b7237-5387-4995-a173-ae87d548e957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303371718 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.3303371718 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_smoke/latest

Test location /workspace/coverage/default/4.kmac_stress_all.3633952253
Short name T552
Test name
Test status
Simulation time 42182339920 ps
CPU time 643.46 seconds
Started Jul 25 05:12:33 PM PDT 24
Finished Jul 25 05:23:17 PM PDT 24
Peak memory 302532 kb
Host smart-6ae3f94d-4ed8-4fbd-b414-25ea05e0658f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3633952253 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.3633952253 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_stress_all/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac.3630459792
Short name T461
Test name
Test status
Simulation time 118114252 ps
CPU time 5.67 seconds
Started Jul 25 05:12:24 PM PDT 24
Finished Jul 25 05:12:30 PM PDT 24
Peak memory 219456 kb
Host smart-bd1c93e1-50a0-4df6-8977-2191ffe1357b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630459792 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.kmac_test_vectors_kmac.3630459792 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac_xof.1588897130
Short name T898
Test name
Test status
Simulation time 520371939 ps
CPU time 6.55 seconds
Started Jul 25 05:12:24 PM PDT 24
Finished Jul 25 05:12:30 PM PDT 24
Peak memory 219432 kb
Host smart-c39f08e4-d2ca-4fee-848b-da0ac978997e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588897130 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.kmac_test_vectors_kmac_xof.1588897130 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_256.2510052088
Short name T829
Test name
Test status
Simulation time 186986388419 ps
CPU time 2125.58 seconds
Started Jul 25 05:12:27 PM PDT 24
Finished Jul 25 05:47:53 PM PDT 24
Peak memory 380240 kb
Host smart-00e8b61b-bdb8-4b6f-8e86-5d0460283c84
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2510052088 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.2510052088 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_384.2947096270
Short name T772
Test name
Test status
Simulation time 69658812997 ps
CPU time 1776.01 seconds
Started Jul 25 05:12:25 PM PDT 24
Finished Jul 25 05:42:01 PM PDT 24
Peak memory 331140 kb
Host smart-11579716-af4b-4648-9c4b-526cf195d92a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2947096270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.2947096270 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_512.3974481869
Short name T1062
Test name
Test status
Simulation time 135194268868 ps
CPU time 1309.48 seconds
Started Jul 25 05:12:27 PM PDT 24
Finished Jul 25 05:34:17 PM PDT 24
Peak memory 303156 kb
Host smart-8f2204c4-3c90-4445-a57b-c8830328c98c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3974481869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.3974481869 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_shake_128.3720347903
Short name T732
Test name
Test status
Simulation time 612845004999 ps
CPU time 5674.09 seconds
Started Jul 25 05:12:24 PM PDT 24
Finished Jul 25 06:46:59 PM PDT 24
Peak memory 660648 kb
Host smart-02acb699-0533-4b8b-8a71-f398c88ff579
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3720347903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.3720347903 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_shake_256.895465063
Short name T709
Test name
Test status
Simulation time 200190324064 ps
CPU time 4205.78 seconds
Started Jul 25 05:12:23 PM PDT 24
Finished Jul 25 06:22:30 PM PDT 24
Peak memory 577532 kb
Host smart-a23149a0-b375-42dc-af89-3f6236a55907
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=895465063 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.895465063 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/40.kmac_alert_test.2082588376
Short name T129
Test name
Test status
Simulation time 71696511 ps
CPU time 0.85 seconds
Started Jul 25 05:18:37 PM PDT 24
Finished Jul 25 05:18:38 PM PDT 24
Peak memory 218280 kb
Host smart-62419292-f22e-488b-b93d-a3911e273ba9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082588376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.2082588376 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_alert_test/latest

Test location /workspace/coverage/default/40.kmac_app.2480342257
Short name T404
Test name
Test status
Simulation time 15512978253 ps
CPU time 378.89 seconds
Started Jul 25 05:18:26 PM PDT 24
Finished Jul 25 05:24:45 PM PDT 24
Peak memory 250916 kb
Host smart-3e0032c1-5864-40af-b26b-541976a4fa7c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480342257 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.2480342257 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/40.kmac_app/latest

Test location /workspace/coverage/default/40.kmac_burst_write.3596351853
Short name T681
Test name
Test status
Simulation time 52127939942 ps
CPU time 1216.53 seconds
Started Jul 25 05:18:26 PM PDT 24
Finished Jul 25 05:38:43 PM PDT 24
Peak memory 239020 kb
Host smart-5fc435e8-28ec-496f-bff4-af284d3e8349
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596351853 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.359635185
3 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_burst_write/latest

Test location /workspace/coverage/default/40.kmac_entropy_refresh.1211607129
Short name T286
Test name
Test status
Simulation time 6399112443 ps
CPU time 289.85 seconds
Started Jul 25 05:18:36 PM PDT 24
Finished Jul 25 05:23:26 PM PDT 24
Peak memory 248060 kb
Host smart-238bbfdd-4d4d-4532-b38e-fefcb08a34da
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211607129 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.1
211607129 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/40.kmac_error.1269976230
Short name T1018
Test name
Test status
Simulation time 6750637828 ps
CPU time 460.99 seconds
Started Jul 25 05:18:38 PM PDT 24
Finished Jul 25 05:26:19 PM PDT 24
Peak memory 268780 kb
Host smart-289b1cb5-9fd7-4191-a4f7-971ccaee904d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269976230 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.1269976230 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_error/latest

Test location /workspace/coverage/default/40.kmac_key_error.1301072625
Short name T119
Test name
Test status
Simulation time 8881543581 ps
CPU time 6.88 seconds
Started Jul 25 05:18:38 PM PDT 24
Finished Jul 25 05:18:45 PM PDT 24
Peak memory 225096 kb
Host smart-362b70c6-d0ca-46e8-b5b5-0e85f7943861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301072625 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.1301072625 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_key_error/latest

Test location /workspace/coverage/default/40.kmac_lc_escalation.618378743
Short name T71
Test name
Test status
Simulation time 55609521 ps
CPU time 1.57 seconds
Started Jul 25 05:18:37 PM PDT 24
Finished Jul 25 05:18:38 PM PDT 24
Peak memory 226572 kb
Host smart-1530b231-77c2-46c2-8818-371f0360612d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618378743 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.618378743 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/40.kmac_lc_escalation/latest

Test location /workspace/coverage/default/40.kmac_long_msg_and_output.3789123550
Short name T571
Test name
Test status
Simulation time 32422954934 ps
CPU time 809.73 seconds
Started Jul 25 05:18:25 PM PDT 24
Finished Jul 25 05:31:55 PM PDT 24
Peak memory 294064 kb
Host smart-6a0240dd-aee9-48a0-b8f7-fa36818d2680
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789123550 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_a
nd_output.3789123550 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/40.kmac_sideload.844436673
Short name T150
Test name
Test status
Simulation time 7481651693 ps
CPU time 178.58 seconds
Started Jul 25 05:18:28 PM PDT 24
Finished Jul 25 05:21:27 PM PDT 24
Peak memory 243092 kb
Host smart-674d5919-d199-484c-bc11-4096e2176b2b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844436673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.844436673 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_sideload/latest

Test location /workspace/coverage/default/40.kmac_smoke.3962216402
Short name T36
Test name
Test status
Simulation time 1979056166 ps
CPU time 76.99 seconds
Started Jul 25 05:18:26 PM PDT 24
Finished Jul 25 05:19:43 PM PDT 24
Peak memory 226680 kb
Host smart-e23b25d7-9429-46ca-9a39-0fc30329c602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962216402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.3962216402 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_smoke/latest

Test location /workspace/coverage/default/40.kmac_stress_all.844606059
Short name T499
Test name
Test status
Simulation time 39227793451 ps
CPU time 1470.43 seconds
Started Jul 25 05:18:37 PM PDT 24
Finished Jul 25 05:43:07 PM PDT 24
Peak memory 351148 kb
Host smart-a5041e7c-adf8-4db6-8418-09867565e1f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=844606059 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.844606059 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_stress_all/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_kmac.1694268285
Short name T669
Test name
Test status
Simulation time 570275597 ps
CPU time 5.86 seconds
Started Jul 25 05:18:29 PM PDT 24
Finished Jul 25 05:18:35 PM PDT 24
Peak memory 219464 kb
Host smart-2321c8dd-1c72-482e-8da4-41d811bd5781
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694268285 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.kmac_test_vectors_kmac.1694268285 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_kmac_xof.3094872579
Short name T747
Test name
Test status
Simulation time 551398425 ps
CPU time 6.08 seconds
Started Jul 25 05:18:28 PM PDT 24
Finished Jul 25 05:18:34 PM PDT 24
Peak memory 218576 kb
Host smart-e4f948c7-3936-49da-9566-e6164404e8de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094872579 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.kmac_test_vectors_kmac_xof.3094872579 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_224.3263963322
Short name T347
Test name
Test status
Simulation time 1634054322243 ps
CPU time 2584.84 seconds
Started Jul 25 05:18:27 PM PDT 24
Finished Jul 25 06:01:32 PM PDT 24
Peak memory 399344 kb
Host smart-2cbf608f-6f67-40f4-8b65-d24616058cc0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3263963322 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_224.3263963322 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_256.1278298317
Short name T794
Test name
Test status
Simulation time 252927617863 ps
CPU time 2244.1 seconds
Started Jul 25 05:18:27 PM PDT 24
Finished Jul 25 05:55:51 PM PDT 24
Peak memory 380052 kb
Host smart-ca6a198d-bab5-4026-94fa-42e8f705510d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1278298317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_256.1278298317 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_384.4142495841
Short name T850
Test name
Test status
Simulation time 116836622405 ps
CPU time 1597.14 seconds
Started Jul 25 05:18:28 PM PDT 24
Finished Jul 25 05:45:06 PM PDT 24
Peak memory 335952 kb
Host smart-7f35dd32-e77d-41af-97ca-82d837ff6b72
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4142495841 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_384.4142495841 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_512.2725225071
Short name T315
Test name
Test status
Simulation time 10574839712 ps
CPU time 1168.17 seconds
Started Jul 25 05:18:28 PM PDT 24
Finished Jul 25 05:37:57 PM PDT 24
Peak memory 297256 kb
Host smart-715650e9-eaa4-496d-a2e7-b4be424532a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2725225071 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_512.2725225071 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_shake_128.3911808570
Short name T934
Test name
Test status
Simulation time 915608802534 ps
CPU time 6169.85 seconds
Started Jul 25 05:18:25 PM PDT 24
Finished Jul 25 07:01:16 PM PDT 24
Peak memory 665348 kb
Host smart-d18b8f50-215f-464b-8d9d-7166198b8022
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3911808570 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_128.3911808570 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_shake_256.3809552570
Short name T1038
Test name
Test status
Simulation time 218485421247 ps
CPU time 4329.47 seconds
Started Jul 25 05:18:25 PM PDT 24
Finished Jul 25 06:30:35 PM PDT 24
Peak memory 569668 kb
Host smart-d1169fd0-d557-4dc2-8237-400c1115f7bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3809552570 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_256.3809552570 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/41.kmac_alert_test.3283897269
Short name T490
Test name
Test status
Simulation time 83041103 ps
CPU time 0.83 seconds
Started Jul 25 05:19:03 PM PDT 24
Finished Jul 25 05:19:04 PM PDT 24
Peak memory 218232 kb
Host smart-f619bd4b-e5eb-4f5c-87f7-74f4b12b8f2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283897269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.3283897269 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_alert_test/latest

Test location /workspace/coverage/default/41.kmac_app.4057994117
Short name T105
Test name
Test status
Simulation time 5638664951 ps
CPU time 125.78 seconds
Started Jul 25 05:19:02 PM PDT 24
Finished Jul 25 05:21:08 PM PDT 24
Peak memory 235144 kb
Host smart-b01dc89c-069c-4813-8ef0-be06562c92f5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057994117 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.4057994117 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/41.kmac_app/latest

Test location /workspace/coverage/default/41.kmac_burst_write.167270369
Short name T513
Test name
Test status
Simulation time 409565582 ps
CPU time 22.36 seconds
Started Jul 25 05:18:53 PM PDT 24
Finished Jul 25 05:19:15 PM PDT 24
Peak memory 226524 kb
Host smart-218f460e-5c3c-42c9-90a4-85b491966237
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167270369 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.167270369
+enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_burst_write/latest

Test location /workspace/coverage/default/41.kmac_entropy_refresh.49355395
Short name T383
Test name
Test status
Simulation time 26458409363 ps
CPU time 361.81 seconds
Started Jul 25 05:19:00 PM PDT 24
Finished Jul 25 05:25:02 PM PDT 24
Peak memory 252840 kb
Host smart-671cc124-5674-4a91-8653-26d59356d163
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49355395 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.493
55395 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/41.kmac_error.387625059
Short name T670
Test name
Test status
Simulation time 16746512233 ps
CPU time 205.49 seconds
Started Jul 25 05:19:01 PM PDT 24
Finished Jul 25 05:22:27 PM PDT 24
Peak memory 251476 kb
Host smart-991f71d3-cf6d-4adf-9f31-846ee94e41c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387625059 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.387625059 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_error/latest

Test location /workspace/coverage/default/41.kmac_key_error.2859774173
Short name T751
Test name
Test status
Simulation time 182701814 ps
CPU time 2.03 seconds
Started Jul 25 05:19:04 PM PDT 24
Finished Jul 25 05:19:07 PM PDT 24
Peak memory 222788 kb
Host smart-78644a35-be25-4770-a609-75e24c5a7ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859774173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.2859774173 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_key_error/latest

Test location /workspace/coverage/default/41.kmac_lc_escalation.2527457403
Short name T58
Test name
Test status
Simulation time 41614434 ps
CPU time 1.42 seconds
Started Jul 25 05:19:00 PM PDT 24
Finished Jul 25 05:19:02 PM PDT 24
Peak memory 226592 kb
Host smart-e8c0081a-8cfb-45a6-955d-2e5238cccaaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527457403 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.2527457403 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/41.kmac_lc_escalation/latest

Test location /workspace/coverage/default/41.kmac_long_msg_and_output.1564467212
Short name T395
Test name
Test status
Simulation time 27424448426 ps
CPU time 367.99 seconds
Started Jul 25 05:18:38 PM PDT 24
Finished Jul 25 05:24:46 PM PDT 24
Peak memory 248724 kb
Host smart-1744a341-a6fc-4100-a497-f1aa83c5baf2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564467212 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_a
nd_output.1564467212 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/41.kmac_sideload.140837683
Short name T653
Test name
Test status
Simulation time 31715665689 ps
CPU time 362.67 seconds
Started Jul 25 05:18:37 PM PDT 24
Finished Jul 25 05:24:40 PM PDT 24
Peak memory 248280 kb
Host smart-74e715ca-3531-4c21-b457-e7b9ad4f5e61
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140837683 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.140837683 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_sideload/latest

Test location /workspace/coverage/default/41.kmac_smoke.3571045475
Short name T237
Test name
Test status
Simulation time 6535954873 ps
CPU time 64.44 seconds
Started Jul 25 05:18:35 PM PDT 24
Finished Jul 25 05:19:40 PM PDT 24
Peak memory 226688 kb
Host smart-7769e5c7-03b3-4616-b002-7143889c2a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571045475 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.3571045475 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_smoke/latest

Test location /workspace/coverage/default/41.kmac_stress_all.2622870411
Short name T568
Test name
Test status
Simulation time 12627286813 ps
CPU time 470.54 seconds
Started Jul 25 05:19:01 PM PDT 24
Finished Jul 25 05:26:51 PM PDT 24
Peak memory 275308 kb
Host smart-dc85f948-4add-4ed9-b87e-1cf3d02f2dc1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2622870411 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.2622870411 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_stress_all/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_kmac.3269421846
Short name T316
Test name
Test status
Simulation time 730998098 ps
CPU time 6.12 seconds
Started Jul 25 05:18:59 PM PDT 24
Finished Jul 25 05:19:06 PM PDT 24
Peak memory 218516 kb
Host smart-3cf17028-2cb7-4927-ac76-234ff7f48c66
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269421846 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.kmac_test_vectors_kmac.3269421846 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_kmac_xof.1740314332
Short name T833
Test name
Test status
Simulation time 120651495 ps
CPU time 5.6 seconds
Started Jul 25 05:19:04 PM PDT 24
Finished Jul 25 05:19:10 PM PDT 24
Peak memory 219540 kb
Host smart-391ad484-fff7-4c54-b18f-1ee6cea615a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740314332 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.kmac_test_vectors_kmac_xof.1740314332 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_256.3406611871
Short name T466
Test name
Test status
Simulation time 19466361090 ps
CPU time 1740.14 seconds
Started Jul 25 05:18:52 PM PDT 24
Finished Jul 25 05:47:52 PM PDT 24
Peak memory 381788 kb
Host smart-6b6e3517-e4ac-4976-90ac-a2255e13e2d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3406611871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_256.3406611871 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_384.2859394972
Short name T895
Test name
Test status
Simulation time 15022922976 ps
CPU time 1461.37 seconds
Started Jul 25 05:18:52 PM PDT 24
Finished Jul 25 05:43:14 PM PDT 24
Peak memory 341856 kb
Host smart-e3ec98e1-e293-4ad6-ac2e-bcd8047615dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2859394972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_384.2859394972 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_512.2490044466
Short name T364
Test name
Test status
Simulation time 11042773691 ps
CPU time 1178.41 seconds
Started Jul 25 05:18:53 PM PDT 24
Finished Jul 25 05:38:31 PM PDT 24
Peak memory 299080 kb
Host smart-94e4c087-16e4-49b3-86f9-9a3b8ed34743
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2490044466 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_512.2490044466 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_shake_128.1426740229
Short name T336
Test name
Test status
Simulation time 61280783719 ps
CPU time 4892.67 seconds
Started Jul 25 05:18:52 PM PDT 24
Finished Jul 25 06:40:25 PM PDT 24
Peak memory 654496 kb
Host smart-dba4b300-ee0c-4440-97f9-b19b76efc113
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1426740229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_128.1426740229 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_shake_256.2907251530
Short name T871
Test name
Test status
Simulation time 293281578329 ps
CPU time 4721 seconds
Started Jul 25 05:18:55 PM PDT 24
Finished Jul 25 06:37:37 PM PDT 24
Peak memory 572488 kb
Host smart-9dd0bfdb-7994-4ac6-a50a-704220f06494
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2907251530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_256.2907251530 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/42.kmac_alert_test.791520266
Short name T797
Test name
Test status
Simulation time 45859186 ps
CPU time 0.75 seconds
Started Jul 25 05:19:19 PM PDT 24
Finished Jul 25 05:19:20 PM PDT 24
Peak memory 218276 kb
Host smart-fcd31686-7029-4095-95aa-4701be17a5c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791520266 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.791520266 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/42.kmac_alert_test/latest

Test location /workspace/coverage/default/42.kmac_app.948274563
Short name T280
Test name
Test status
Simulation time 4690275676 ps
CPU time 133.19 seconds
Started Jul 25 05:19:09 PM PDT 24
Finished Jul 25 05:21:23 PM PDT 24
Peak memory 236460 kb
Host smart-38943b36-5c5f-4711-9860-ae38baa7821b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948274563 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.948274563 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/42.kmac_app/latest

Test location /workspace/coverage/default/42.kmac_burst_write.2570655692
Short name T780
Test name
Test status
Simulation time 24502721050 ps
CPU time 474.29 seconds
Started Jul 25 05:19:02 PM PDT 24
Finished Jul 25 05:26:56 PM PDT 24
Peak memory 233324 kb
Host smart-a79fb1ca-7454-44de-ae0d-0fa8cffdcf53
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570655692 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.257065569
2 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_burst_write/latest

Test location /workspace/coverage/default/42.kmac_entropy_refresh.1233756443
Short name T183
Test name
Test status
Simulation time 15900658794 ps
CPU time 329.44 seconds
Started Jul 25 05:19:10 PM PDT 24
Finished Jul 25 05:24:39 PM PDT 24
Peak memory 246588 kb
Host smart-1a52fdd5-7a0a-4dcb-a22a-c17388ccbd77
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233756443 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.1
233756443 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/42.kmac_error.3847529083
Short name T915
Test name
Test status
Simulation time 16387126492 ps
CPU time 409.08 seconds
Started Jul 25 05:19:11 PM PDT 24
Finished Jul 25 05:26:00 PM PDT 24
Peak memory 259356 kb
Host smart-a7c97674-879c-4a81-811c-aafa3943b831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847529083 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.3847529083 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_error/latest

Test location /workspace/coverage/default/42.kmac_key_error.2167035040
Short name T509
Test name
Test status
Simulation time 6705953882 ps
CPU time 11.4 seconds
Started Jul 25 05:19:07 PM PDT 24
Finished Jul 25 05:19:19 PM PDT 24
Peak memory 225312 kb
Host smart-15279b99-1a89-474f-9162-2fc4b5f16389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167035040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.2167035040 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_key_error/latest

Test location /workspace/coverage/default/42.kmac_lc_escalation.3785823900
Short name T712
Test name
Test status
Simulation time 160031896 ps
CPU time 1.54 seconds
Started Jul 25 05:19:09 PM PDT 24
Finished Jul 25 05:19:11 PM PDT 24
Peak memory 226540 kb
Host smart-5bb65687-19da-427a-8bf3-40292e04ea30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785823900 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.3785823900 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/42.kmac_lc_escalation/latest

Test location /workspace/coverage/default/42.kmac_long_msg_and_output.357199929
Short name T544
Test name
Test status
Simulation time 108910817408 ps
CPU time 497.71 seconds
Started Jul 25 05:19:06 PM PDT 24
Finished Jul 25 05:27:23 PM PDT 24
Peak memory 257552 kb
Host smart-dfa8f1dc-5153-4bd0-b8c8-dcf57c4d231d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357199929 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_an
d_output.357199929 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/42.kmac_sideload.1899800666
Short name T130
Test name
Test status
Simulation time 8311497730 ps
CPU time 140.02 seconds
Started Jul 25 05:19:16 PM PDT 24
Finished Jul 25 05:21:37 PM PDT 24
Peak memory 235064 kb
Host smart-c0fdec63-8a58-488d-adf2-d3a84cfba7c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899800666 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.1899800666 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_sideload/latest

Test location /workspace/coverage/default/42.kmac_smoke.3707405263
Short name T894
Test name
Test status
Simulation time 1855837840 ps
CPU time 76.24 seconds
Started Jul 25 05:19:05 PM PDT 24
Finished Jul 25 05:20:22 PM PDT 24
Peak memory 222476 kb
Host smart-596bdd9e-7668-4220-905b-b696d685e0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707405263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.3707405263 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_smoke/latest

Test location /workspace/coverage/default/42.kmac_stress_all.2796650137
Short name T330
Test name
Test status
Simulation time 903159385 ps
CPU time 39.58 seconds
Started Jul 25 05:19:17 PM PDT 24
Finished Jul 25 05:19:57 PM PDT 24
Peak memory 237132 kb
Host smart-dbe968e5-0534-45b8-9898-23218457270b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2796650137 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.2796650137 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_stress_all/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_kmac.914109827
Short name T768
Test name
Test status
Simulation time 243965996 ps
CPU time 6.05 seconds
Started Jul 25 05:19:16 PM PDT 24
Finished Jul 25 05:19:23 PM PDT 24
Peak memory 219456 kb
Host smart-a871271e-c379-49a4-b306-9c96120c47ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914109827 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.kmac_test_vectors_kmac.914109827 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_kmac_xof.3605991021
Short name T425
Test name
Test status
Simulation time 181882650 ps
CPU time 6.03 seconds
Started Jul 25 05:19:15 PM PDT 24
Finished Jul 25 05:19:21 PM PDT 24
Peak memory 218592 kb
Host smart-10877a8f-8be5-4d85-b0ed-a664bf5a1402
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605991021 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.kmac_test_vectors_kmac_xof.3605991021 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_224.3439334303
Short name T840
Test name
Test status
Simulation time 88160596056 ps
CPU time 1992.01 seconds
Started Jul 25 05:19:01 PM PDT 24
Finished Jul 25 05:52:13 PM PDT 24
Peak memory 389160 kb
Host smart-c0d70be8-d258-4688-bb7b-49e053c06a4f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3439334303 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_224.3439334303 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_256.1007209325
Short name T452
Test name
Test status
Simulation time 26328132127 ps
CPU time 1940.66 seconds
Started Jul 25 05:19:01 PM PDT 24
Finished Jul 25 05:51:22 PM PDT 24
Peak memory 388420 kb
Host smart-fdc09224-3374-4841-9aeb-b13233ae2aba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1007209325 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_256.1007209325 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_384.163084047
Short name T899
Test name
Test status
Simulation time 59720420344 ps
CPU time 1504.35 seconds
Started Jul 25 05:19:07 PM PDT 24
Finished Jul 25 05:44:12 PM PDT 24
Peak memory 340140 kb
Host smart-564f8ba4-ad9c-48bb-8412-4c4e9c2ed28e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=163084047 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_384.163084047 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_512.3431414723
Short name T478
Test name
Test status
Simulation time 10631503242 ps
CPU time 1068.05 seconds
Started Jul 25 05:19:02 PM PDT 24
Finished Jul 25 05:36:51 PM PDT 24
Peak memory 297444 kb
Host smart-4c00ed59-5a7a-44d5-903d-dfc0842cc35e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3431414723 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_512.3431414723 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_shake_128.3747552211
Short name T53
Test name
Test status
Simulation time 708987349933 ps
CPU time 5713.31 seconds
Started Jul 25 05:19:01 PM PDT 24
Finished Jul 25 06:54:15 PM PDT 24
Peak memory 654496 kb
Host smart-bc32bab9-fddd-4615-b2e1-f2eb63ad1b76
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3747552211 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_128.3747552211 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_shake_256.563252634
Short name T525
Test name
Test status
Simulation time 891334525113 ps
CPU time 4354.47 seconds
Started Jul 25 05:19:16 PM PDT 24
Finished Jul 25 06:31:51 PM PDT 24
Peak memory 569916 kb
Host smart-450670c0-aec8-4e11-89a8-b8699d6aa6dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=563252634 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_256.563252634 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/43.kmac_alert_test.3384566600
Short name T648
Test name
Test status
Simulation time 25564683 ps
CPU time 0.83 seconds
Started Jul 25 05:19:31 PM PDT 24
Finished Jul 25 05:19:32 PM PDT 24
Peak memory 218228 kb
Host smart-044df2dc-655f-4eb4-a8c6-3d93c7ca097c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384566600 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.3384566600 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_alert_test/latest

Test location /workspace/coverage/default/43.kmac_app.3207425258
Short name T371
Test name
Test status
Simulation time 9622048514 ps
CPU time 228.02 seconds
Started Jul 25 05:19:27 PM PDT 24
Finished Jul 25 05:23:15 PM PDT 24
Peak memory 244256 kb
Host smart-a2200906-a91c-4ab2-b92d-501542a0617c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207425258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.3207425258 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/43.kmac_app/latest

Test location /workspace/coverage/default/43.kmac_burst_write.2829258344
Short name T643
Test name
Test status
Simulation time 18909066151 ps
CPU time 858.93 seconds
Started Jul 25 05:19:18 PM PDT 24
Finished Jul 25 05:33:38 PM PDT 24
Peak memory 236628 kb
Host smart-4b763009-101d-40ea-abe9-873311ade535
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829258344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.282925834
4 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_burst_write/latest

Test location /workspace/coverage/default/43.kmac_entropy_refresh.3110975286
Short name T485
Test name
Test status
Simulation time 4276022106 ps
CPU time 152.92 seconds
Started Jul 25 05:19:28 PM PDT 24
Finished Jul 25 05:22:02 PM PDT 24
Peak memory 239364 kb
Host smart-8aeb1f1a-c701-443f-acd7-a963d0495c46
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110975286 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.3
110975286 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/43.kmac_error.2669505971
Short name T860
Test name
Test status
Simulation time 17158923287 ps
CPU time 200.93 seconds
Started Jul 25 05:19:25 PM PDT 24
Finished Jul 25 05:22:46 PM PDT 24
Peak memory 259148 kb
Host smart-54058a69-2996-433b-8170-a943fa8e6b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669505971 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.2669505971 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_error/latest

Test location /workspace/coverage/default/43.kmac_key_error.1555968084
Short name T277
Test name
Test status
Simulation time 1263536269 ps
CPU time 4.45 seconds
Started Jul 25 05:19:26 PM PDT 24
Finished Jul 25 05:19:31 PM PDT 24
Peak memory 222832 kb
Host smart-8d816053-c040-4d57-9598-5b824fb0a77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555968084 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.1555968084 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_key_error/latest

Test location /workspace/coverage/default/43.kmac_lc_escalation.3862291242
Short name T708
Test name
Test status
Simulation time 28224336 ps
CPU time 1.32 seconds
Started Jul 25 05:19:26 PM PDT 24
Finished Jul 25 05:19:28 PM PDT 24
Peak memory 226560 kb
Host smart-90f58c85-4b48-4425-b5ac-3bc30220383e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862291242 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.3862291242 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/43.kmac_lc_escalation/latest

Test location /workspace/coverage/default/43.kmac_long_msg_and_output.4192233281
Short name T464
Test name
Test status
Simulation time 10374817268 ps
CPU time 1157.64 seconds
Started Jul 25 05:19:21 PM PDT 24
Finished Jul 25 05:38:39 PM PDT 24
Peak memory 319032 kb
Host smart-275d508c-c660-4ad3-bc91-84d56c09b42d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192233281 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_a
nd_output.4192233281 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/43.kmac_sideload.3483418316
Short name T507
Test name
Test status
Simulation time 31775413529 ps
CPU time 337.76 seconds
Started Jul 25 05:19:16 PM PDT 24
Finished Jul 25 05:24:54 PM PDT 24
Peak memory 249496 kb
Host smart-79599af0-39f7-490c-a257-7306b09eb93b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483418316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.3483418316 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_sideload/latest

Test location /workspace/coverage/default/43.kmac_smoke.345200663
Short name T306
Test name
Test status
Simulation time 3235460837 ps
CPU time 80.33 seconds
Started Jul 25 05:19:18 PM PDT 24
Finished Jul 25 05:20:39 PM PDT 24
Peak memory 226652 kb
Host smart-09153a7b-d866-4107-9a49-006d966159b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345200663 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.345200663 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_smoke/latest

Test location /workspace/coverage/default/43.kmac_stress_all.593293387
Short name T1023
Test name
Test status
Simulation time 9339029916 ps
CPU time 86 seconds
Started Jul 25 05:19:31 PM PDT 24
Finished Jul 25 05:20:57 PM PDT 24
Peak memory 254748 kb
Host smart-961c13e3-c326-4c1f-99a3-e0ccb9a17e4f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=593293387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.593293387 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_stress_all/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_kmac.4005457436
Short name T278
Test name
Test status
Simulation time 861041582 ps
CPU time 6.12 seconds
Started Jul 25 05:19:18 PM PDT 24
Finished Jul 25 05:19:24 PM PDT 24
Peak memory 218596 kb
Host smart-0df5cd7b-79dd-4a62-b862-3f07aca62d62
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005457436 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.kmac_test_vectors_kmac.4005457436 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_kmac_xof.2174985652
Short name T867
Test name
Test status
Simulation time 779674072 ps
CPU time 6.12 seconds
Started Jul 25 05:19:17 PM PDT 24
Finished Jul 25 05:19:23 PM PDT 24
Peak memory 219476 kb
Host smart-4317200c-0552-4c78-b98e-fa7a47c78991
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174985652 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.kmac_test_vectors_kmac_xof.2174985652 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_224.1057762865
Short name T942
Test name
Test status
Simulation time 135873096411 ps
CPU time 2267.54 seconds
Started Jul 25 05:19:23 PM PDT 24
Finished Jul 25 05:57:11 PM PDT 24
Peak memory 395216 kb
Host smart-d12496fa-0e2d-47d2-a1a6-381560a3288d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1057762865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_224.1057762865 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_256.3530323074
Short name T1052
Test name
Test status
Simulation time 399854726294 ps
CPU time 2212.27 seconds
Started Jul 25 05:19:21 PM PDT 24
Finished Jul 25 05:56:13 PM PDT 24
Peak memory 392324 kb
Host smart-0af2b558-08b1-410d-b2e0-41df375f686c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3530323074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_256.3530323074 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_384.3280979045
Short name T232
Test name
Test status
Simulation time 289872998038 ps
CPU time 1798.39 seconds
Started Jul 25 05:19:17 PM PDT 24
Finished Jul 25 05:49:15 PM PDT 24
Peak memory 336140 kb
Host smart-c0f6e706-13a8-4e67-aebc-9f43185b8c2c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3280979045 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_384.3280979045 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_512.3569894139
Short name T893
Test name
Test status
Simulation time 11226752411 ps
CPU time 1239.44 seconds
Started Jul 25 05:19:19 PM PDT 24
Finished Jul 25 05:39:58 PM PDT 24
Peak memory 300248 kb
Host smart-595268a2-64a1-4993-a600-7d7d89d819f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3569894139 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_512.3569894139 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_shake_128.3608517427
Short name T929
Test name
Test status
Simulation time 71383055840 ps
CPU time 4842.04 seconds
Started Jul 25 05:19:18 PM PDT 24
Finished Jul 25 06:40:01 PM PDT 24
Peak memory 654748 kb
Host smart-202a8b94-2f84-46b4-9208-171342446ebe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3608517427 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_128.3608517427 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_shake_256.3383089148
Short name T124
Test name
Test status
Simulation time 889977207951 ps
CPU time 5071.9 seconds
Started Jul 25 05:19:18 PM PDT 24
Finished Jul 25 06:43:51 PM PDT 24
Peak memory 580912 kb
Host smart-9979e72f-5e18-4ac0-ab3e-fe4100a0ffab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3383089148 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_256.3383089148 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/44.kmac_alert_test.395411668
Short name T443
Test name
Test status
Simulation time 15312748 ps
CPU time 0.81 seconds
Started Jul 25 05:19:44 PM PDT 24
Finished Jul 25 05:19:45 PM PDT 24
Peak memory 218272 kb
Host smart-e49e630b-5ad8-4311-b830-541a4c8c9188
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395411668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.395411668 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/44.kmac_alert_test/latest

Test location /workspace/coverage/default/44.kmac_app.3069246432
Short name T602
Test name
Test status
Simulation time 4823070190 ps
CPU time 309.37 seconds
Started Jul 25 05:19:37 PM PDT 24
Finished Jul 25 05:24:46 PM PDT 24
Peak memory 248308 kb
Host smart-2ff4e972-8c2c-4d3c-ba5a-738726aa3cab
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069246432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.3069246432 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/44.kmac_app/latest

Test location /workspace/coverage/default/44.kmac_burst_write.3161807112
Short name T1006
Test name
Test status
Simulation time 16374920239 ps
CPU time 852.29 seconds
Started Jul 25 05:19:41 PM PDT 24
Finished Jul 25 05:33:54 PM PDT 24
Peak memory 243112 kb
Host smart-162961ad-60ef-4de0-acb1-48ac24e75131
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161807112 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.316180711
2 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_burst_write/latest

Test location /workspace/coverage/default/44.kmac_entropy_refresh.1612301088
Short name T351
Test name
Test status
Simulation time 7548937685 ps
CPU time 117.71 seconds
Started Jul 25 05:19:44 PM PDT 24
Finished Jul 25 05:21:42 PM PDT 24
Peak memory 235040 kb
Host smart-3b438313-4f17-4bc8-9aff-ba639692476c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612301088 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.1
612301088 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/44.kmac_error.1763862347
Short name T715
Test name
Test status
Simulation time 444178964 ps
CPU time 39.19 seconds
Started Jul 25 05:19:45 PM PDT 24
Finished Jul 25 05:20:25 PM PDT 24
Peak memory 242920 kb
Host smart-f1d89e24-0872-4912-99a1-ab7b8320bbad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763862347 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.1763862347 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_error/latest

Test location /workspace/coverage/default/44.kmac_key_error.739701991
Short name T907
Test name
Test status
Simulation time 106657006 ps
CPU time 1.49 seconds
Started Jul 25 05:19:46 PM PDT 24
Finished Jul 25 05:19:47 PM PDT 24
Peak memory 222120 kb
Host smart-f3408fc3-dca6-4ad0-99c5-7ef5342da53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739701991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.739701991 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_key_error/latest

Test location /workspace/coverage/default/44.kmac_lc_escalation.2276818439
Short name T15
Test name
Test status
Simulation time 132872406 ps
CPU time 1.43 seconds
Started Jul 25 05:19:44 PM PDT 24
Finished Jul 25 05:19:45 PM PDT 24
Peak memory 226500 kb
Host smart-1833b7c2-aa02-4485-9ad3-eed2c02c1c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276818439 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.2276818439 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/44.kmac_lc_escalation/latest

Test location /workspace/coverage/default/44.kmac_long_msg_and_output.1601227118
Short name T523
Test name
Test status
Simulation time 90397130904 ps
CPU time 941.4 seconds
Started Jul 25 05:19:35 PM PDT 24
Finished Jul 25 05:35:17 PM PDT 24
Peak memory 287472 kb
Host smart-52272877-2e8b-471d-b753-7dc19e9685e1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601227118 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_a
nd_output.1601227118 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/44.kmac_sideload.479429402
Short name T323
Test name
Test status
Simulation time 12052432935 ps
CPU time 472.63 seconds
Started Jul 25 05:19:36 PM PDT 24
Finished Jul 25 05:27:28 PM PDT 24
Peak memory 255488 kb
Host smart-a98de0e2-b89e-4222-8f90-24ac7319d779
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479429402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.479429402 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_sideload/latest

Test location /workspace/coverage/default/44.kmac_smoke.3579114285
Short name T1071
Test name
Test status
Simulation time 4609518548 ps
CPU time 78.31 seconds
Started Jul 25 05:19:31 PM PDT 24
Finished Jul 25 05:20:49 PM PDT 24
Peak memory 222988 kb
Host smart-547442bc-6ee7-4418-bb81-578239941faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579114285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.3579114285 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_smoke/latest

Test location /workspace/coverage/default/44.kmac_stress_all.1351055603
Short name T635
Test name
Test status
Simulation time 16241126125 ps
CPU time 284.48 seconds
Started Jul 25 05:19:44 PM PDT 24
Finished Jul 25 05:24:28 PM PDT 24
Peak memory 274940 kb
Host smart-45392b87-6f4f-4255-84ad-a5d4d7288c17
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1351055603 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.1351055603 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_stress_all/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_kmac.2145160522
Short name T1034
Test name
Test status
Simulation time 252390935 ps
CPU time 6.47 seconds
Started Jul 25 05:19:36 PM PDT 24
Finished Jul 25 05:19:42 PM PDT 24
Peak memory 218592 kb
Host smart-c595fb81-3379-42e1-b8c8-d5be2e6978af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145160522 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.kmac_test_vectors_kmac.2145160522 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_kmac_xof.4167984465
Short name T645
Test name
Test status
Simulation time 825071817 ps
CPU time 6.18 seconds
Started Jul 25 05:19:38 PM PDT 24
Finished Jul 25 05:19:45 PM PDT 24
Peak memory 218536 kb
Host smart-f6c34856-2ac9-43f9-af78-7a94421d8fb0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167984465 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.kmac_test_vectors_kmac_xof.4167984465 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_224.2405843074
Short name T338
Test name
Test status
Simulation time 100103408423 ps
CPU time 2355.99 seconds
Started Jul 25 05:19:35 PM PDT 24
Finished Jul 25 05:58:51 PM PDT 24
Peak memory 404012 kb
Host smart-3eb3368f-b6a9-48c5-b087-a02493f7ba7a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2405843074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_224.2405843074 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_256.685548671
Short name T122
Test name
Test status
Simulation time 62043777640 ps
CPU time 2147.65 seconds
Started Jul 25 05:19:42 PM PDT 24
Finished Jul 25 05:55:30 PM PDT 24
Peak memory 384380 kb
Host smart-75f38ce9-e466-4e86-89a4-8d20c3f3f9e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=685548671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_256.685548671 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_384.546720429
Short name T963
Test name
Test status
Simulation time 259976634588 ps
CPU time 1903.07 seconds
Started Jul 25 05:19:37 PM PDT 24
Finished Jul 25 05:51:20 PM PDT 24
Peak memory 340376 kb
Host smart-73914080-6c8b-4091-bb2e-598f111eb9a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=546720429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_384.546720429 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_512.444754371
Short name T652
Test name
Test status
Simulation time 11217128484 ps
CPU time 1091.62 seconds
Started Jul 25 05:19:36 PM PDT 24
Finished Jul 25 05:37:48 PM PDT 24
Peak memory 296752 kb
Host smart-4896039e-46e5-4a1b-8231-9307ba416cda
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=444754371 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_512.444754371 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_shake_128.43151884
Short name T398
Test name
Test status
Simulation time 180711953286 ps
CPU time 5161.86 seconds
Started Jul 25 05:19:51 PM PDT 24
Finished Jul 25 06:45:53 PM PDT 24
Peak memory 640156 kb
Host smart-6a8785a2-cda7-48a3-a7fe-feb4d8b94fb5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=43151884 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_128.43151884 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_shake_256.1841837973
Short name T882
Test name
Test status
Simulation time 114011650196 ps
CPU time 4278.87 seconds
Started Jul 25 05:19:36 PM PDT 24
Finished Jul 25 06:30:56 PM PDT 24
Peak memory 564776 kb
Host smart-34a2eced-ec94-435d-b8a3-15dcc7e0e5bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1841837973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_256.1841837973 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/45.kmac_alert_test.4229889674
Short name T1005
Test name
Test status
Simulation time 134472903 ps
CPU time 0.89 seconds
Started Jul 25 05:20:02 PM PDT 24
Finished Jul 25 05:20:03 PM PDT 24
Peak memory 218188 kb
Host smart-096ce093-ca03-44c8-b748-719285a7a706
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229889674 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.4229889674 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_alert_test/latest

Test location /workspace/coverage/default/45.kmac_burst_write.4118626519
Short name T41
Test name
Test status
Simulation time 18305269826 ps
CPU time 813.23 seconds
Started Jul 25 05:19:45 PM PDT 24
Finished Jul 25 05:33:19 PM PDT 24
Peak memory 236004 kb
Host smart-dde2144e-0005-4126-b59d-0d228bb7d88d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118626519 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.411862651
9 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_burst_write/latest

Test location /workspace/coverage/default/45.kmac_entropy_refresh.261015884
Short name T762
Test name
Test status
Simulation time 18480414725 ps
CPU time 95.83 seconds
Started Jul 25 05:19:51 PM PDT 24
Finished Jul 25 05:21:27 PM PDT 24
Peak memory 239672 kb
Host smart-cb14aeaf-f3aa-4abf-bae2-9ca7772caa22
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261015884 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.26
1015884 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/45.kmac_error.4291908650
Short name T25
Test name
Test status
Simulation time 6061681844 ps
CPU time 173.75 seconds
Started Jul 25 05:19:53 PM PDT 24
Finished Jul 25 05:22:47 PM PDT 24
Peak memory 251248 kb
Host smart-29ee48d3-70f6-4080-829f-f1f212e8a170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291908650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.4291908650 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_error/latest

Test location /workspace/coverage/default/45.kmac_key_error.2118749117
Short name T749
Test name
Test status
Simulation time 254474352 ps
CPU time 2.42 seconds
Started Jul 25 05:19:54 PM PDT 24
Finished Jul 25 05:19:57 PM PDT 24
Peak memory 218432 kb
Host smart-5d7709dc-079f-4356-a884-e2f246627442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118749117 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.2118749117 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_key_error/latest

Test location /workspace/coverage/default/45.kmac_lc_escalation.4133379459
Short name T74
Test name
Test status
Simulation time 142989540 ps
CPU time 1.43 seconds
Started Jul 25 05:19:52 PM PDT 24
Finished Jul 25 05:19:54 PM PDT 24
Peak memory 226636 kb
Host smart-f401218f-ee94-4f4c-a4b5-ff86be8828eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133379459 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.4133379459 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/45.kmac_lc_escalation/latest

Test location /workspace/coverage/default/45.kmac_long_msg_and_output.364436836
Short name T822
Test name
Test status
Simulation time 228100609850 ps
CPU time 1737.99 seconds
Started Jul 25 05:19:44 PM PDT 24
Finished Jul 25 05:48:42 PM PDT 24
Peak memory 374848 kb
Host smart-75a62421-adc8-4288-95a8-c7e247c5ead8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364436836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_an
d_output.364436836 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/45.kmac_sideload.998873295
Short name T601
Test name
Test status
Simulation time 4664397013 ps
CPU time 422.29 seconds
Started Jul 25 05:19:44 PM PDT 24
Finished Jul 25 05:26:46 PM PDT 24
Peak memory 251356 kb
Host smart-481ebd0d-460e-4048-99c3-cbdb04e06cb6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998873295 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.998873295 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_sideload/latest

Test location /workspace/coverage/default/45.kmac_smoke.1857159713
Short name T484
Test name
Test status
Simulation time 2569467406 ps
CPU time 24.84 seconds
Started Jul 25 05:19:45 PM PDT 24
Finished Jul 25 05:20:10 PM PDT 24
Peak memory 218664 kb
Host smart-bbfdb0fa-fce6-43b2-9860-3b771fb15af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857159713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.1857159713 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_smoke/latest

Test location /workspace/coverage/default/45.kmac_stress_all.3609036469
Short name T83
Test name
Test status
Simulation time 31920980436 ps
CPU time 1000.56 seconds
Started Jul 25 05:20:04 PM PDT 24
Finished Jul 25 05:36:44 PM PDT 24
Peak memory 307128 kb
Host smart-42a1ca93-0be6-4b77-9288-6af32c9b937e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3609036469 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.3609036469 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_stress_all/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_kmac.1392211036
Short name T264
Test name
Test status
Simulation time 994418750 ps
CPU time 6.23 seconds
Started Jul 25 05:19:45 PM PDT 24
Finished Jul 25 05:19:52 PM PDT 24
Peak memory 218592 kb
Host smart-25e940cd-e9bb-44d4-aef0-7a6cb0da37cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392211036 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.kmac_test_vectors_kmac.1392211036 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_kmac_xof.3139229876
Short name T970
Test name
Test status
Simulation time 1064746986 ps
CPU time 6.51 seconds
Started Jul 25 05:19:53 PM PDT 24
Finished Jul 25 05:19:59 PM PDT 24
Peak memory 218652 kb
Host smart-a7e3e2fa-872a-4703-ba89-79f54ece84dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139229876 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.kmac_test_vectors_kmac_xof.3139229876 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_224.3106354063
Short name T606
Test name
Test status
Simulation time 308899347657 ps
CPU time 2306.78 seconds
Started Jul 25 05:19:45 PM PDT 24
Finished Jul 25 05:58:12 PM PDT 24
Peak memory 393600 kb
Host smart-f7a302b0-fec1-4f84-b9fd-d6feea1bab95
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3106354063 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_224.3106354063 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_256.1156624074
Short name T213
Test name
Test status
Simulation time 302628839447 ps
CPU time 2065.06 seconds
Started Jul 25 05:19:45 PM PDT 24
Finished Jul 25 05:54:11 PM PDT 24
Peak memory 379736 kb
Host smart-6d212c72-2391-4bde-a0cc-29ce984e2989
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1156624074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_256.1156624074 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_384.2722405506
Short name T728
Test name
Test status
Simulation time 282881717479 ps
CPU time 1660.59 seconds
Started Jul 25 05:19:46 PM PDT 24
Finished Jul 25 05:47:27 PM PDT 24
Peak memory 341380 kb
Host smart-83238fcf-2213-47d0-8d30-02b65cdf43fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2722405506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_384.2722405506 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_512.1689782420
Short name T778
Test name
Test status
Simulation time 50128001059 ps
CPU time 1445.39 seconds
Started Jul 25 05:19:46 PM PDT 24
Finished Jul 25 05:43:51 PM PDT 24
Peak memory 303064 kb
Host smart-45206268-9e7b-4e94-932f-2a979a319fd9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1689782420 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_512.1689782420 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_shake_128.326929756
Short name T807
Test name
Test status
Simulation time 2414269060844 ps
CPU time 5361.05 seconds
Started Jul 25 05:19:44 PM PDT 24
Finished Jul 25 06:49:05 PM PDT 24
Peak memory 650440 kb
Host smart-81da7bed-36c4-428d-8b15-bd019e224ca9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=326929756 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_128.326929756 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_shake_256.858830439
Short name T516
Test name
Test status
Simulation time 54313897513 ps
CPU time 4202.11 seconds
Started Jul 25 05:19:46 PM PDT 24
Finished Jul 25 06:29:49 PM PDT 24
Peak memory 567952 kb
Host smart-40c2f3c2-9fef-47d6-b7b3-0085dde849b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=858830439 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_256.858830439 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/46.kmac_alert_test.3190881361
Short name T689
Test name
Test status
Simulation time 30081475 ps
CPU time 0.85 seconds
Started Jul 25 05:20:10 PM PDT 24
Finished Jul 25 05:20:11 PM PDT 24
Peak memory 218284 kb
Host smart-0d8749a7-24f9-4604-a31c-1465595fff8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190881361 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.3190881361 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_alert_test/latest

Test location /workspace/coverage/default/46.kmac_app.2520940432
Short name T704
Test name
Test status
Simulation time 164823884 ps
CPU time 9.81 seconds
Started Jul 25 05:20:10 PM PDT 24
Finished Jul 25 05:20:20 PM PDT 24
Peak memory 226628 kb
Host smart-df6f4f1f-e50f-44bb-a4e5-409a348478ac
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520940432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.2520940432 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/46.kmac_app/latest

Test location /workspace/coverage/default/46.kmac_burst_write.1158141138
Short name T905
Test name
Test status
Simulation time 14248752510 ps
CPU time 512.68 seconds
Started Jul 25 05:20:02 PM PDT 24
Finished Jul 25 05:28:35 PM PDT 24
Peak memory 232504 kb
Host smart-e623673e-314f-4b33-ba60-9c35e7546496
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158141138 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.115814113
8 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_burst_write/latest

Test location /workspace/coverage/default/46.kmac_error.362952276
Short name T674
Test name
Test status
Simulation time 72039202181 ps
CPU time 248.93 seconds
Started Jul 25 05:20:11 PM PDT 24
Finished Jul 25 05:24:20 PM PDT 24
Peak memory 259444 kb
Host smart-f29b54b6-7a39-40e7-a1b4-683966e23aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362952276 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.362952276 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_error/latest

Test location /workspace/coverage/default/46.kmac_key_error.838754039
Short name T288
Test name
Test status
Simulation time 1220890117 ps
CPU time 5.94 seconds
Started Jul 25 05:20:10 PM PDT 24
Finished Jul 25 05:20:16 PM PDT 24
Peak memory 223364 kb
Host smart-17a183c0-a14d-4cb3-bdb2-0b200c9eeb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838754039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.838754039 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_key_error/latest

Test location /workspace/coverage/default/46.kmac_lc_escalation.3484225403
Short name T29
Test name
Test status
Simulation time 96818040 ps
CPU time 1.29 seconds
Started Jul 25 05:20:10 PM PDT 24
Finished Jul 25 05:20:11 PM PDT 24
Peak memory 226588 kb
Host smart-edbdd9b1-d2cb-44bc-b3c4-d500a828c9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484225403 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.3484225403 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/46.kmac_lc_escalation/latest

Test location /workspace/coverage/default/46.kmac_long_msg_and_output.1478192892
Short name T522
Test name
Test status
Simulation time 88708625935 ps
CPU time 2248.54 seconds
Started Jul 25 05:20:02 PM PDT 24
Finished Jul 25 05:57:31 PM PDT 24
Peak memory 432416 kb
Host smart-395f25c9-58d1-4ef9-9bd2-532728bc3d4d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478192892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_a
nd_output.1478192892 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/46.kmac_sideload.2257636538
Short name T770
Test name
Test status
Simulation time 1495584256 ps
CPU time 24.12 seconds
Started Jul 25 05:20:02 PM PDT 24
Finished Jul 25 05:20:26 PM PDT 24
Peak memory 226876 kb
Host smart-1faa3648-6d3c-4fab-b1aa-5541f2bf3dec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257636538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.2257636538 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_sideload/latest

Test location /workspace/coverage/default/46.kmac_smoke.1128899837
Short name T402
Test name
Test status
Simulation time 4118129740 ps
CPU time 49.39 seconds
Started Jul 25 05:20:03 PM PDT 24
Finished Jul 25 05:20:53 PM PDT 24
Peak memory 218612 kb
Host smart-ce855076-6b29-42cd-8b82-b19dee644a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128899837 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.1128899837 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_smoke/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_kmac.510930941
Short name T273
Test name
Test status
Simulation time 512269448 ps
CPU time 6.28 seconds
Started Jul 25 05:20:03 PM PDT 24
Finished Jul 25 05:20:09 PM PDT 24
Peak memory 218616 kb
Host smart-f237afc9-2270-4ba7-bdf2-a69169c6b42e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510930941 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.kmac_test_vectors_kmac.510930941 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_kmac_xof.1540627283
Short name T322
Test name
Test status
Simulation time 133222145 ps
CPU time 5.48 seconds
Started Jul 25 05:20:10 PM PDT 24
Finished Jul 25 05:20:16 PM PDT 24
Peak memory 219488 kb
Host smart-a1eb93d0-787e-46f5-9c1d-1b26393070f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540627283 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.kmac_test_vectors_kmac_xof.1540627283 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_224.143931298
Short name T369
Test name
Test status
Simulation time 134069249266 ps
CPU time 2078.14 seconds
Started Jul 25 05:20:02 PM PDT 24
Finished Jul 25 05:54:40 PM PDT 24
Peak memory 398084 kb
Host smart-631055a3-ba92-4fec-bbda-f1214db3739f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=143931298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_224.143931298 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_256.3598919517
Short name T945
Test name
Test status
Simulation time 99217836529 ps
CPU time 2332.69 seconds
Started Jul 25 05:20:02 PM PDT 24
Finished Jul 25 05:58:55 PM PDT 24
Peak memory 395872 kb
Host smart-7932ddc0-42cf-458e-babc-50aa0f664886
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3598919517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_256.3598919517 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_384.3641301517
Short name T227
Test name
Test status
Simulation time 540578445462 ps
CPU time 2037.9 seconds
Started Jul 25 05:20:03 PM PDT 24
Finished Jul 25 05:54:01 PM PDT 24
Peak memory 340392 kb
Host smart-a0f2adf3-3565-4512-80f1-8bae5cf365c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3641301517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_384.3641301517 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_512.1930245928
Short name T386
Test name
Test status
Simulation time 22433317406 ps
CPU time 1050.51 seconds
Started Jul 25 05:20:01 PM PDT 24
Finished Jul 25 05:37:32 PM PDT 24
Peak memory 301056 kb
Host smart-78ff571a-8fed-4c67-8035-80dbf1abf279
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1930245928 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_512.1930245928 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_shake_128.895452512
Short name T554
Test name
Test status
Simulation time 72441518761 ps
CPU time 4803.11 seconds
Started Jul 25 05:20:02 PM PDT 24
Finished Jul 25 06:40:06 PM PDT 24
Peak memory 655380 kb
Host smart-58b7fe20-8ed4-4491-9da5-1441615add8e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=895452512 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_128.895452512 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_shake_256.2881713384
Short name T976
Test name
Test status
Simulation time 154011540927 ps
CPU time 4569.88 seconds
Started Jul 25 05:20:03 PM PDT 24
Finished Jul 25 06:36:13 PM PDT 24
Peak memory 561320 kb
Host smart-94588526-5b54-49f8-a946-e9179645ab91
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2881713384 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_256.2881713384 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/47.kmac_alert_test.2732674759
Short name T847
Test name
Test status
Simulation time 278896077 ps
CPU time 0.93 seconds
Started Jul 25 05:20:39 PM PDT 24
Finished Jul 25 05:20:40 PM PDT 24
Peak memory 218232 kb
Host smart-44bfb30f-e733-4984-aed0-2d67a2ed8acd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732674759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.2732674759 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_alert_test/latest

Test location /workspace/coverage/default/47.kmac_burst_write.4079552871
Short name T368
Test name
Test status
Simulation time 96319950577 ps
CPU time 883.68 seconds
Started Jul 25 05:20:18 PM PDT 24
Finished Jul 25 05:35:02 PM PDT 24
Peak memory 243052 kb
Host smart-bb014216-5838-4f82-874b-e73ddfbe4268
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079552871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.407955287
1 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_burst_write/latest

Test location /workspace/coverage/default/47.kmac_entropy_refresh.1929886171
Short name T1072
Test name
Test status
Simulation time 36977812148 ps
CPU time 356.99 seconds
Started Jul 25 05:20:26 PM PDT 24
Finished Jul 25 05:26:23 PM PDT 24
Peak memory 252500 kb
Host smart-75545532-60a9-41e3-bc36-7d5a7232597f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929886171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.1
929886171 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/47.kmac_error.3567875724
Short name T361
Test name
Test status
Simulation time 21701408657 ps
CPU time 359.17 seconds
Started Jul 25 05:20:26 PM PDT 24
Finished Jul 25 05:26:26 PM PDT 24
Peak memory 252524 kb
Host smart-66be5cd4-eba5-4077-bb20-1de591525112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567875724 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.3567875724 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_error/latest

Test location /workspace/coverage/default/47.kmac_key_error.141456625
Short name T577
Test name
Test status
Simulation time 1336343182 ps
CPU time 11.06 seconds
Started Jul 25 05:20:30 PM PDT 24
Finished Jul 25 05:20:41 PM PDT 24
Peak memory 224652 kb
Host smart-1c34521f-fd2e-4cdd-98ee-260718f30059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141456625 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.141456625 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_key_error/latest

Test location /workspace/coverage/default/47.kmac_lc_escalation.2513284088
Short name T30
Test name
Test status
Simulation time 65142771 ps
CPU time 1.32 seconds
Started Jul 25 05:20:28 PM PDT 24
Finished Jul 25 05:20:29 PM PDT 24
Peak memory 226644 kb
Host smart-2d9714fd-ce26-44a2-b7b5-164e15ec0f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513284088 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.2513284088 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/47.kmac_lc_escalation/latest

Test location /workspace/coverage/default/47.kmac_long_msg_and_output.3201196504
Short name T869
Test name
Test status
Simulation time 101534638287 ps
CPU time 2701.84 seconds
Started Jul 25 05:20:11 PM PDT 24
Finished Jul 25 06:05:13 PM PDT 24
Peak memory 457776 kb
Host smart-a5d651c3-316a-4e45-871d-3fed2a8936f8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201196504 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_a
nd_output.3201196504 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/47.kmac_sideload.4054644031
Short name T980
Test name
Test status
Simulation time 174308984 ps
CPU time 6.62 seconds
Started Jul 25 05:20:19 PM PDT 24
Finished Jul 25 05:20:26 PM PDT 24
Peak memory 220112 kb
Host smart-fff44e0c-8456-4fb3-a823-b47d147d4daa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054644031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.4054644031 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_sideload/latest

Test location /workspace/coverage/default/47.kmac_smoke.2156410890
Short name T727
Test name
Test status
Simulation time 530693966 ps
CPU time 12.85 seconds
Started Jul 25 05:20:11 PM PDT 24
Finished Jul 25 05:20:24 PM PDT 24
Peak memory 223496 kb
Host smart-896e69f6-ec9a-4e87-9b22-298a8143e45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156410890 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.2156410890 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_smoke/latest

Test location /workspace/coverage/default/47.kmac_stress_all.2347535682
Short name T1032
Test name
Test status
Simulation time 39330291271 ps
CPU time 1355.54 seconds
Started Jul 25 05:20:29 PM PDT 24
Finished Jul 25 05:43:05 PM PDT 24
Peak memory 390664 kb
Host smart-1ed13a11-da66-4e5a-b513-4f859fe1ee99
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2347535682 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.2347535682 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_stress_all/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_kmac.2233017263
Short name T848
Test name
Test status
Simulation time 542607452 ps
CPU time 6.74 seconds
Started Jul 25 05:20:29 PM PDT 24
Finished Jul 25 05:20:36 PM PDT 24
Peak memory 218520 kb
Host smart-9187662c-7830-48d7-bb40-24a175c363ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233017263 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.kmac_test_vectors_kmac.2233017263 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_kmac_xof.3312415609
Short name T147
Test name
Test status
Simulation time 268182474 ps
CPU time 6.24 seconds
Started Jul 25 05:20:30 PM PDT 24
Finished Jul 25 05:20:37 PM PDT 24
Peak memory 219460 kb
Host smart-2dec6316-4989-4336-bfa4-856df744497a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312415609 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.kmac_test_vectors_kmac_xof.3312415609 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_224.4162997337
Short name T332
Test name
Test status
Simulation time 91918314251 ps
CPU time 1997.78 seconds
Started Jul 25 05:20:19 PM PDT 24
Finished Jul 25 05:53:37 PM PDT 24
Peak memory 394212 kb
Host smart-c26078cc-14b8-4007-a2a4-c3fb27bf8c19
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4162997337 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_224.4162997337 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_256.1051532483
Short name T283
Test name
Test status
Simulation time 20032587823 ps
CPU time 1916.61 seconds
Started Jul 25 05:20:18 PM PDT 24
Finished Jul 25 05:52:15 PM PDT 24
Peak memory 386000 kb
Host smart-724c43ea-3e9a-4cf9-9983-e9d09dbc3d94
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1051532483 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_256.1051532483 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_384.389157068
Short name T600
Test name
Test status
Simulation time 282857013393 ps
CPU time 1946.85 seconds
Started Jul 25 05:20:18 PM PDT 24
Finished Jul 25 05:52:46 PM PDT 24
Peak memory 341804 kb
Host smart-e4f62c22-cef4-49a8-a8d8-17cca776ecbb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=389157068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_384.389157068 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_512.1979374435
Short name T382
Test name
Test status
Simulation time 43346774792 ps
CPU time 1153.88 seconds
Started Jul 25 05:20:18 PM PDT 24
Finished Jul 25 05:39:32 PM PDT 24
Peak memory 298324 kb
Host smart-6bea090e-18aa-4c0f-9b05-5f69f92f5bdd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1979374435 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_512.1979374435 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_shake_128.1353260460
Short name T438
Test name
Test status
Simulation time 121379096599 ps
CPU time 5027.35 seconds
Started Jul 25 05:20:18 PM PDT 24
Finished Jul 25 06:44:06 PM PDT 24
Peak memory 644708 kb
Host smart-d71eda19-fb47-429d-b026-ca8e7754e118
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1353260460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_128.1353260460 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_shake_256.3729945390
Short name T348
Test name
Test status
Simulation time 594975846143 ps
CPU time 4895.11 seconds
Started Jul 25 05:20:29 PM PDT 24
Finished Jul 25 06:42:05 PM PDT 24
Peak memory 559324 kb
Host smart-9d2a254c-07ae-4afe-8acd-07dbf1d929bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3729945390 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_256.3729945390 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/48.kmac_alert_test.447502795
Short name T936
Test name
Test status
Simulation time 17438507 ps
CPU time 0.82 seconds
Started Jul 25 05:20:54 PM PDT 24
Finished Jul 25 05:20:55 PM PDT 24
Peak memory 218212 kb
Host smart-e2654bcc-e608-4bd3-b706-c61371ce46ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447502795 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.447502795 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/48.kmac_alert_test/latest

Test location /workspace/coverage/default/48.kmac_app.2625807775
Short name T771
Test name
Test status
Simulation time 17796169054 ps
CPU time 235.01 seconds
Started Jul 25 05:20:46 PM PDT 24
Finished Jul 25 05:24:41 PM PDT 24
Peak memory 245316 kb
Host smart-56c2bf40-106d-42e4-9eb6-cf1c27b8eda3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625807775 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.2625807775 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/48.kmac_app/latest

Test location /workspace/coverage/default/48.kmac_burst_write.1423564577
Short name T686
Test name
Test status
Simulation time 115224669436 ps
CPU time 611.22 seconds
Started Jul 25 05:20:36 PM PDT 24
Finished Jul 25 05:30:47 PM PDT 24
Peak memory 234736 kb
Host smart-64640203-0857-4e8e-9615-df4e61f6d231
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423564577 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.142356457
7 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_burst_write/latest

Test location /workspace/coverage/default/48.kmac_entropy_refresh.1238608650
Short name T1031
Test name
Test status
Simulation time 15134578992 ps
CPU time 181.04 seconds
Started Jul 25 05:20:44 PM PDT 24
Finished Jul 25 05:23:45 PM PDT 24
Peak memory 239368 kb
Host smart-9c17af6f-e03b-48b5-8357-670062e93004
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238608650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.1
238608650 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/48.kmac_error.3635497513
Short name T255
Test name
Test status
Simulation time 980494858 ps
CPU time 66.63 seconds
Started Jul 25 05:20:44 PM PDT 24
Finished Jul 25 05:21:51 PM PDT 24
Peak memory 238440 kb
Host smart-d55a60e2-1298-4901-b56d-06e846c5c1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635497513 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.3635497513 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_error/latest

Test location /workspace/coverage/default/48.kmac_key_error.855661917
Short name T107
Test name
Test status
Simulation time 1618806461 ps
CPU time 4.55 seconds
Started Jul 25 05:20:43 PM PDT 24
Finished Jul 25 05:20:48 PM PDT 24
Peak memory 223060 kb
Host smart-bababc27-c1ef-42ec-8791-324f76a02902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855661917 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.855661917 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_key_error/latest

Test location /workspace/coverage/default/48.kmac_lc_escalation.3127808653
Short name T1004
Test name
Test status
Simulation time 69049348 ps
CPU time 1.51 seconds
Started Jul 25 05:20:53 PM PDT 24
Finished Jul 25 05:20:55 PM PDT 24
Peak memory 226688 kb
Host smart-284f4941-e4b5-4994-ab26-87ce95ff3bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127808653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.3127808653 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/48.kmac_lc_escalation/latest

Test location /workspace/coverage/default/48.kmac_long_msg_and_output.1446686476
Short name T260
Test name
Test status
Simulation time 78595296196 ps
CPU time 2746.94 seconds
Started Jul 25 05:20:37 PM PDT 24
Finished Jul 25 06:06:24 PM PDT 24
Peak memory 441108 kb
Host smart-79ee3210-89df-4f04-a1ad-0c9f4c04c51b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446686476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_a
nd_output.1446686476 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/48.kmac_sideload.3337127027
Short name T432
Test name
Test status
Simulation time 20591348453 ps
CPU time 487.81 seconds
Started Jul 25 05:20:34 PM PDT 24
Finished Jul 25 05:28:42 PM PDT 24
Peak memory 256344 kb
Host smart-163f3ff2-d37c-47d3-8b61-d9f7f9f4fbf8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337127027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.3337127027 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_sideload/latest

Test location /workspace/coverage/default/48.kmac_smoke.201519360
Short name T598
Test name
Test status
Simulation time 10700726302 ps
CPU time 81.52 seconds
Started Jul 25 05:20:35 PM PDT 24
Finished Jul 25 05:21:57 PM PDT 24
Peak memory 222384 kb
Host smart-6a6f96cc-f3fd-40f0-8519-d4ffc9a4a57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201519360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.201519360 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_smoke/latest

Test location /workspace/coverage/default/48.kmac_stress_all.2560310381
Short name T937
Test name
Test status
Simulation time 28512455738 ps
CPU time 234.67 seconds
Started Jul 25 05:21:10 PM PDT 24
Finished Jul 25 05:25:05 PM PDT 24
Peak memory 257044 kb
Host smart-da6deb38-5a54-499b-98f8-71272144fae2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2560310381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.2560310381 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_stress_all/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_kmac.4260752438
Short name T977
Test name
Test status
Simulation time 720210714 ps
CPU time 6.49 seconds
Started Jul 25 05:20:37 PM PDT 24
Finished Jul 25 05:20:44 PM PDT 24
Peak memory 218540 kb
Host smart-1f4d0561-84a8-44e1-b014-ec37b52c9818
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260752438 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.kmac_test_vectors_kmac.4260752438 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_kmac_xof.4271157384
Short name T1014
Test name
Test status
Simulation time 227499555 ps
CPU time 6.57 seconds
Started Jul 25 05:20:45 PM PDT 24
Finished Jul 25 05:20:52 PM PDT 24
Peak memory 218516 kb
Host smart-31b0489f-edee-4233-9846-ce966766d38c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271157384 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.kmac_test_vectors_kmac_xof.4271157384 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_224.3422596404
Short name T2
Test name
Test status
Simulation time 196649784960 ps
CPU time 2389.28 seconds
Started Jul 25 05:20:37 PM PDT 24
Finished Jul 25 06:00:27 PM PDT 24
Peak memory 394588 kb
Host smart-4f9cc127-0086-4e85-9661-2e19a6fa78c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3422596404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_224.3422596404 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_256.2239157483
Short name T616
Test name
Test status
Simulation time 70744984294 ps
CPU time 2139.07 seconds
Started Jul 25 05:20:37 PM PDT 24
Finished Jul 25 05:56:16 PM PDT 24
Peak memory 391760 kb
Host smart-2df7837b-b5e2-4df6-b1f9-4b4ac3b9dcc5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2239157483 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_256.2239157483 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_512.2450343798
Short name T707
Test name
Test status
Simulation time 53259476254 ps
CPU time 1198.85 seconds
Started Jul 25 05:20:35 PM PDT 24
Finished Jul 25 05:40:34 PM PDT 24
Peak memory 296196 kb
Host smart-6276cafd-cef2-4d1a-969c-418457e6507e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2450343798 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_512.2450343798 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_shake_256.2264962210
Short name T1054
Test name
Test status
Simulation time 903371985072 ps
CPU time 5438.6 seconds
Started Jul 25 05:20:36 PM PDT 24
Finished Jul 25 06:51:16 PM PDT 24
Peak memory 567536 kb
Host smart-45512cb5-e36b-4fe8-91d4-3cf819c02e87
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2264962210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_256.2264962210 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/49.kmac_alert_test.1881057682
Short name T247
Test name
Test status
Simulation time 24097301 ps
CPU time 0.88 seconds
Started Jul 25 05:21:10 PM PDT 24
Finished Jul 25 05:21:11 PM PDT 24
Peak memory 218268 kb
Host smart-6335bab8-68c2-4fc9-9cfd-fdb20087b7c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881057682 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.1881057682 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_alert_test/latest

Test location /workspace/coverage/default/49.kmac_app.3954771948
Short name T938
Test name
Test status
Simulation time 2918250936 ps
CPU time 70 seconds
Started Jul 25 05:21:04 PM PDT 24
Finished Jul 25 05:22:14 PM PDT 24
Peak memory 228412 kb
Host smart-91ea67dd-2078-4c3a-9e91-56e3dc661589
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954771948 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.3954771948 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/49.kmac_app/latest

Test location /workspace/coverage/default/49.kmac_burst_write.2633696377
Short name T472
Test name
Test status
Simulation time 12030108801 ps
CPU time 1159.83 seconds
Started Jul 25 05:20:52 PM PDT 24
Finished Jul 25 05:40:12 PM PDT 24
Peak memory 237124 kb
Host smart-f5b45129-a47d-43fa-ba56-5c68639f9a9e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633696377 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.263369637
7 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_burst_write/latest

Test location /workspace/coverage/default/49.kmac_entropy_refresh.1134737518
Short name T289
Test name
Test status
Simulation time 1104812205 ps
CPU time 40 seconds
Started Jul 25 05:21:03 PM PDT 24
Finished Jul 25 05:21:43 PM PDT 24
Peak memory 226832 kb
Host smart-3c234cd2-b89a-4585-bcff-e01f54e8263c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134737518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.1
134737518 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/49.kmac_error.948149402
Short name T442
Test name
Test status
Simulation time 27091594946 ps
CPU time 348.87 seconds
Started Jul 25 05:21:11 PM PDT 24
Finished Jul 25 05:27:00 PM PDT 24
Peak memory 259416 kb
Host smart-9406bdff-c1fc-4fa6-b440-8ee809e4e62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948149402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.948149402 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_error/latest

Test location /workspace/coverage/default/49.kmac_key_error.2121350482
Short name T990
Test name
Test status
Simulation time 5016329485 ps
CPU time 8.12 seconds
Started Jul 25 05:21:10 PM PDT 24
Finished Jul 25 05:21:18 PM PDT 24
Peak memory 224660 kb
Host smart-09ff77dd-701b-41b9-b8eb-5b3d9a302dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121350482 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.2121350482 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_key_error/latest

Test location /workspace/coverage/default/49.kmac_lc_escalation.3157148492
Short name T73
Test name
Test status
Simulation time 100837922 ps
CPU time 1.16 seconds
Started Jul 25 05:21:12 PM PDT 24
Finished Jul 25 05:21:13 PM PDT 24
Peak memory 226624 kb
Host smart-957ba45b-e295-4073-9a5f-d11761a5091c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157148492 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.3157148492 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/49.kmac_lc_escalation/latest

Test location /workspace/coverage/default/49.kmac_long_msg_and_output.3446828576
Short name T696
Test name
Test status
Simulation time 30404158907 ps
CPU time 824 seconds
Started Jul 25 05:20:53 PM PDT 24
Finished Jul 25 05:34:38 PM PDT 24
Peak memory 281164 kb
Host smart-322905e7-fa8e-4958-bb83-2a33246caa01
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446828576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_a
nd_output.3446828576 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/49.kmac_sideload.3765671149
Short name T1059
Test name
Test status
Simulation time 356045919 ps
CPU time 8.11 seconds
Started Jul 25 05:20:54 PM PDT 24
Finished Jul 25 05:21:02 PM PDT 24
Peak memory 225604 kb
Host smart-89bb13fe-74ff-4ca5-8b84-9493e8cf2289
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765671149 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.3765671149 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_sideload/latest

Test location /workspace/coverage/default/49.kmac_smoke.1432603876
Short name T788
Test name
Test status
Simulation time 2299925191 ps
CPU time 26.62 seconds
Started Jul 25 05:20:54 PM PDT 24
Finished Jul 25 05:21:21 PM PDT 24
Peak memory 222376 kb
Host smart-bf86061f-60ff-4f7f-9873-3803db4b0824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432603876 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.1432603876 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_smoke/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_kmac.1859765719
Short name T651
Test name
Test status
Simulation time 174910226 ps
CPU time 6.26 seconds
Started Jul 25 05:24:36 PM PDT 24
Finished Jul 25 05:24:42 PM PDT 24
Peak memory 218576 kb
Host smart-b9be3126-5244-40fe-8da7-afbafa6e4c5f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859765719 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.kmac_test_vectors_kmac.1859765719 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_kmac_xof.3047421045
Short name T424
Test name
Test status
Simulation time 195991681 ps
CPU time 5.91 seconds
Started Jul 25 05:21:06 PM PDT 24
Finished Jul 25 05:21:12 PM PDT 24
Peak memory 218572 kb
Host smart-f1b980a0-f283-4750-9b66-baa0fa6a7933
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047421045 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.kmac_test_vectors_kmac_xof.3047421045 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_224.3634337494
Short name T581
Test name
Test status
Simulation time 42289016498 ps
CPU time 2092.23 seconds
Started Jul 25 05:20:51 PM PDT 24
Finished Jul 25 05:55:44 PM PDT 24
Peak memory 393884 kb
Host smart-81563f24-c129-47a5-ac8d-b3d3698c003e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3634337494 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_224.3634337494 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_256.1861086048
Short name T1043
Test name
Test status
Simulation time 122782382219 ps
CPU time 2111.06 seconds
Started Jul 25 05:21:05 PM PDT 24
Finished Jul 25 05:56:16 PM PDT 24
Peak memory 382200 kb
Host smart-3e2a1ddf-ee36-4813-89ea-1a44e2e20797
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1861086048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_256.1861086048 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_384.2946687868
Short name T387
Test name
Test status
Simulation time 15134403246 ps
CPU time 1505.17 seconds
Started Jul 25 05:21:06 PM PDT 24
Finished Jul 25 05:46:11 PM PDT 24
Peak memory 333552 kb
Host smart-89a683c2-cd53-4e11-af65-247809eb86cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2946687868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_384.2946687868 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_512.3251753687
Short name T504
Test name
Test status
Simulation time 44039565473 ps
CPU time 1248.69 seconds
Started Jul 25 05:21:05 PM PDT 24
Finished Jul 25 05:41:54 PM PDT 24
Peak memory 303272 kb
Host smart-9d037a31-514c-401b-98b2-42740c7031b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3251753687 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_512.3251753687 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_shake_128.1071893699
Short name T333
Test name
Test status
Simulation time 190429030133 ps
CPU time 5436.86 seconds
Started Jul 25 05:21:05 PM PDT 24
Finished Jul 25 06:51:43 PM PDT 24
Peak memory 669844 kb
Host smart-50343fc3-2feb-4363-aed0-f21b2fb9dfa0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1071893699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_128.1071893699 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_shake_256.468023854
Short name T701
Test name
Test status
Simulation time 608318425454 ps
CPU time 5061.57 seconds
Started Jul 25 05:21:05 PM PDT 24
Finished Jul 25 06:45:27 PM PDT 24
Peak memory 571932 kb
Host smart-df7d061b-430a-4402-b392-075613ecc142
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=468023854 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_256.468023854 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/5.kmac_alert_test.3048319284
Short name T613
Test name
Test status
Simulation time 45621052 ps
CPU time 0.87 seconds
Started Jul 25 05:12:30 PM PDT 24
Finished Jul 25 05:12:31 PM PDT 24
Peak memory 218284 kb
Host smart-051148b5-06d8-4249-954f-c154581e5a6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048319284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.3048319284 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_alert_test/latest

Test location /workspace/coverage/default/5.kmac_app.314498953
Short name T290
Test name
Test status
Simulation time 6444062236 ps
CPU time 164.82 seconds
Started Jul 25 05:12:27 PM PDT 24
Finished Jul 25 05:15:12 PM PDT 24
Peak memory 239660 kb
Host smart-7e7fc9ce-0814-421f-b79f-f6d0fb9e36bf
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314498953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.314498953 +enable_masking=1
+sw_key_masked=0
Directory /workspace/5.kmac_app/latest

Test location /workspace/coverage/default/5.kmac_app_with_partial_data.1603425413
Short name T844
Test name
Test status
Simulation time 76515965893 ps
CPU time 222.04 seconds
Started Jul 25 05:12:26 PM PDT 24
Finished Jul 25 05:16:08 PM PDT 24
Peak memory 241236 kb
Host smart-3add4019-e252-4600-82b4-c5e3f0527765
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603425413 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_par
tial_data.1603425413 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/5.kmac_burst_write.2580152732
Short name T320
Test name
Test status
Simulation time 6863541378 ps
CPU time 687.05 seconds
Started Jul 25 05:12:27 PM PDT 24
Finished Jul 25 05:23:54 PM PDT 24
Peak memory 233692 kb
Host smart-80aa7e0a-7ad0-4e51-bb58-fbb525810390
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580152732 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.2580152732
+enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_burst_write/latest

Test location /workspace/coverage/default/5.kmac_edn_timeout_error.2329486117
Short name T363
Test name
Test status
Simulation time 763865548 ps
CPU time 11.64 seconds
Started Jul 25 05:12:24 PM PDT 24
Finished Jul 25 05:12:36 PM PDT 24
Peak memory 226340 kb
Host smart-45b9fd93-b756-49a1-982f-c8d0c74f4d89
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2329486117 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.2329486117 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_mode_error.1556932850
Short name T396
Test name
Test status
Simulation time 25464898 ps
CPU time 1.02 seconds
Started Jul 25 05:12:28 PM PDT 24
Finished Jul 25 05:12:29 PM PDT 24
Peak memory 221920 kb
Host smart-89ed3a8e-fc78-40e1-960a-5d799967bd5a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1556932850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.1556932850 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_ready_error.1394469290
Short name T10
Test name
Test status
Simulation time 2734216871 ps
CPU time 32.16 seconds
Started Jul 25 05:12:30 PM PDT 24
Finished Jul 25 05:13:02 PM PDT 24
Peak memory 218660 kb
Host smart-52707561-7710-4c9f-aa98-8577ec55b652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394469290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.1394469290 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_refresh.2734443006
Short name T81
Test name
Test status
Simulation time 24884437972 ps
CPU time 253.52 seconds
Started Jul 25 05:12:28 PM PDT 24
Finished Jul 25 05:16:42 PM PDT 24
Peak memory 243412 kb
Host smart-02b566ed-d9fd-4921-9f11-ef2bbbd84af8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734443006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.27
34443006 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/5.kmac_error.3181564277
Short name T631
Test name
Test status
Simulation time 22816422537 ps
CPU time 439.9 seconds
Started Jul 25 05:12:31 PM PDT 24
Finished Jul 25 05:19:51 PM PDT 24
Peak memory 258580 kb
Host smart-3efe06e2-f837-4cd5-a83a-e0a2ea1be4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181564277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.3181564277 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_error/latest

Test location /workspace/coverage/default/5.kmac_key_error.3238250817
Short name T468
Test name
Test status
Simulation time 1031329893 ps
CPU time 7.99 seconds
Started Jul 25 05:12:30 PM PDT 24
Finished Jul 25 05:12:38 PM PDT 24
Peak memory 223024 kb
Host smart-92bcb22a-64ae-4fbf-9cc1-66cd5ed4d89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238250817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.3238250817 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_key_error/latest

Test location /workspace/coverage/default/5.kmac_lc_escalation.3077918364
Short name T69
Test name
Test status
Simulation time 168023139 ps
CPU time 1.36 seconds
Started Jul 25 05:12:30 PM PDT 24
Finished Jul 25 05:12:32 PM PDT 24
Peak memory 226620 kb
Host smart-8d2ec209-1f50-4844-9008-4344099eea8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077918364 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.3077918364 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/5.kmac_lc_escalation/latest

Test location /workspace/coverage/default/5.kmac_long_msg_and_output.355203495
Short name T821
Test name
Test status
Simulation time 60155155487 ps
CPU time 2036.55 seconds
Started Jul 25 05:12:28 PM PDT 24
Finished Jul 25 05:46:25 PM PDT 24
Peak memory 391708 kb
Host smart-d1c87eda-86d9-4a95-986c-868337dd4c00
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355203495 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_and
_output.355203495 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/5.kmac_mubi.248801147
Short name T370
Test name
Test status
Simulation time 18313200577 ps
CPU time 264.91 seconds
Started Jul 25 05:12:26 PM PDT 24
Finished Jul 25 05:16:51 PM PDT 24
Peak memory 247704 kb
Host smart-721dea98-a75e-462d-9beb-50e72f0381bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248801147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.248801147 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_mubi/latest

Test location /workspace/coverage/default/5.kmac_sideload.215501307
Short name T311
Test name
Test status
Simulation time 33737509653 ps
CPU time 196.01 seconds
Started Jul 25 05:12:24 PM PDT 24
Finished Jul 25 05:15:41 PM PDT 24
Peak memory 238616 kb
Host smart-8cc27298-c1b8-4208-a371-fc0e7b3a1a3e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215501307 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.215501307 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_sideload/latest

Test location /workspace/coverage/default/5.kmac_smoke.1315811334
Short name T800
Test name
Test status
Simulation time 118689627 ps
CPU time 5.49 seconds
Started Jul 25 05:12:26 PM PDT 24
Finished Jul 25 05:12:31 PM PDT 24
Peak memory 219644 kb
Host smart-0450d623-cdaa-439c-933a-0dea36a96e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315811334 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.1315811334 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_smoke/latest

Test location /workspace/coverage/default/5.kmac_stress_all.3553224655
Short name T948
Test name
Test status
Simulation time 66734313575 ps
CPU time 848 seconds
Started Jul 25 05:12:27 PM PDT 24
Finished Jul 25 05:26:36 PM PDT 24
Peak memory 308992 kb
Host smart-bb4fd3c4-7d47-4fe8-ac7e-dc43179ef24f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3553224655 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.3553224655 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_stress_all/latest

Test location /workspace/coverage/default/5.kmac_stress_all_with_rand_reset.854004095
Short name T48
Test name
Test status
Simulation time 20246972190 ps
CPU time 417.63 seconds
Started Jul 25 05:12:37 PM PDT 24
Finished Jul 25 05:19:35 PM PDT 24
Peak memory 269976 kb
Host smart-e5965e6b-3d5a-4a9a-9837-7126ab7ee511
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=854004095 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all_with_rand_reset.854004095 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_kmac.499197371
Short name T698
Test name
Test status
Simulation time 347506633 ps
CPU time 5.64 seconds
Started Jul 25 05:12:26 PM PDT 24
Finished Jul 25 05:12:32 PM PDT 24
Peak memory 218568 kb
Host smart-5a215db1-6561-4329-82f3-88aeb4dc1b21
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499197371 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.kmac_test_vectors_kmac.499197371 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_kmac_xof.1949190249
Short name T281
Test name
Test status
Simulation time 577124109 ps
CPU time 6.97 seconds
Started Jul 25 05:12:28 PM PDT 24
Finished Jul 25 05:12:35 PM PDT 24
Peak memory 218548 kb
Host smart-1db0115b-02c2-4b98-89a0-407c9fb73e05
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949190249 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.kmac_test_vectors_kmac_xof.1949190249 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_224.1265966675
Short name T967
Test name
Test status
Simulation time 84113499730 ps
CPU time 1891.14 seconds
Started Jul 25 05:12:26 PM PDT 24
Finished Jul 25 05:43:58 PM PDT 24
Peak memory 398252 kb
Host smart-28135b58-21ac-480c-a467-9ba615167381
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1265966675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_224.1265966675 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_256.1860190347
Short name T888
Test name
Test status
Simulation time 79648329110 ps
CPU time 2235.88 seconds
Started Jul 25 05:12:25 PM PDT 24
Finished Jul 25 05:49:41 PM PDT 24
Peak memory 382400 kb
Host smart-e1a7db95-0afa-4f04-b023-2e25bf8f944a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1860190347 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_256.1860190347 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_384.503678594
Short name T310
Test name
Test status
Simulation time 14971924899 ps
CPU time 1374.89 seconds
Started Jul 25 05:12:25 PM PDT 24
Finished Jul 25 05:35:20 PM PDT 24
Peak memory 338252 kb
Host smart-a112e304-0e1f-49e3-a936-d13a9f389bb4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=503678594 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_384.503678594 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_512.884287053
Short name T561
Test name
Test status
Simulation time 33025540296 ps
CPU time 1187.52 seconds
Started Jul 25 05:12:26 PM PDT 24
Finished Jul 25 05:32:14 PM PDT 24
Peak memory 300012 kb
Host smart-2d9e9ae4-1e58-48f8-99ed-20bc9b76a57b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=884287053 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_512.884287053 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_shake_128.730148892
Short name T841
Test name
Test status
Simulation time 452058865921 ps
CPU time 5784.83 seconds
Started Jul 25 05:12:28 PM PDT 24
Finished Jul 25 06:48:54 PM PDT 24
Peak memory 651416 kb
Host smart-4914a471-7950-4a3b-8bd1-fcf5a73a5f1a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=730148892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_128.730148892 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_shake_256.2281138048
Short name T558
Test name
Test status
Simulation time 109665240409 ps
CPU time 4340.99 seconds
Started Jul 25 05:12:26 PM PDT 24
Finished Jul 25 06:24:47 PM PDT 24
Peak memory 573996 kb
Host smart-b4181844-7581-4bf3-8672-e60fa014bf8d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2281138048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_256.2281138048 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/6.kmac_alert_test.2325573089
Short name T115
Test name
Test status
Simulation time 80978242 ps
CPU time 0.84 seconds
Started Jul 25 05:12:52 PM PDT 24
Finished Jul 25 05:12:53 PM PDT 24
Peak memory 218236 kb
Host smart-d0d14e71-9450-4034-bf87-71a4205e85f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325573089 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.2325573089 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_alert_test/latest

Test location /workspace/coverage/default/6.kmac_app.3682870736
Short name T971
Test name
Test status
Simulation time 13562424113 ps
CPU time 405.07 seconds
Started Jul 25 05:12:39 PM PDT 24
Finished Jul 25 05:19:24 PM PDT 24
Peak memory 253808 kb
Host smart-641dd2ea-4e66-4a96-9613-b67644acc5c1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682870736 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.3682870736 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/6.kmac_app/latest

Test location /workspace/coverage/default/6.kmac_app_with_partial_data.3872844352
Short name T559
Test name
Test status
Simulation time 3377548658 ps
CPU time 119.86 seconds
Started Jul 25 05:12:41 PM PDT 24
Finished Jul 25 05:14:41 PM PDT 24
Peak memory 235244 kb
Host smart-fc6268e0-5c16-42b2-b96e-049128465711
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872844352 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_par
tial_data.3872844352 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/6.kmac_burst_write.356722774
Short name T585
Test name
Test status
Simulation time 4237925765 ps
CPU time 446.48 seconds
Started Jul 25 05:12:30 PM PDT 24
Finished Jul 25 05:19:56 PM PDT 24
Peak memory 230616 kb
Host smart-aad7ba2c-1ac3-46e2-8d19-0c96fe4ac431
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356722774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.356722774 +
enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_burst_write/latest

Test location /workspace/coverage/default/6.kmac_edn_timeout_error.2846471798
Short name T431
Test name
Test status
Simulation time 1915716324 ps
CPU time 43.05 seconds
Started Jul 25 05:12:41 PM PDT 24
Finished Jul 25 05:13:24 PM PDT 24
Peak memory 227048 kb
Host smart-65a2a78e-f0d1-4790-a02a-faa90febc254
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2846471798 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.2846471798 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_mode_error.2388341080
Short name T1055
Test name
Test status
Simulation time 134858310 ps
CPU time 1.28 seconds
Started Jul 25 05:12:40 PM PDT 24
Finished Jul 25 05:12:41 PM PDT 24
Peak memory 222212 kb
Host smart-5b08f5d3-96a0-4daa-aeae-1ed102ad3cf3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2388341080 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.2388341080 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_ready_error.2300840499
Short name T12
Test name
Test status
Simulation time 7633046206 ps
CPU time 52.56 seconds
Started Jul 25 05:12:35 PM PDT 24
Finished Jul 25 05:13:28 PM PDT 24
Peak memory 220448 kb
Host smart-e50e242f-71f7-4f22-9f50-7f655b2c3e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300840499 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.2300840499 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_refresh.864579149
Short name T1041
Test name
Test status
Simulation time 59026489554 ps
CPU time 353.86 seconds
Started Jul 25 05:12:41 PM PDT 24
Finished Jul 25 05:18:36 PM PDT 24
Peak memory 251388 kb
Host smart-bcad9e66-1d74-4482-84cf-33ef4d7a439e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864579149 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.864
579149 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/6.kmac_error.2460311811
Short name T955
Test name
Test status
Simulation time 54701451022 ps
CPU time 147.29 seconds
Started Jul 25 05:12:38 PM PDT 24
Finished Jul 25 05:15:06 PM PDT 24
Peak memory 251296 kb
Host smart-a418270c-4434-4ff3-bc46-0efc16d6678a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460311811 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.2460311811 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_error/latest

Test location /workspace/coverage/default/6.kmac_key_error.2378920568
Short name T730
Test name
Test status
Simulation time 935682343 ps
CPU time 7.58 seconds
Started Jul 25 05:12:39 PM PDT 24
Finished Jul 25 05:12:47 PM PDT 24
Peak memory 223204 kb
Host smart-e78541e6-0a98-466a-98ca-f3b1167867d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378920568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.2378920568 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_key_error/latest

Test location /workspace/coverage/default/6.kmac_lc_escalation.3841634389
Short name T629
Test name
Test status
Simulation time 159706783 ps
CPU time 1.37 seconds
Started Jul 25 05:12:41 PM PDT 24
Finished Jul 25 05:12:43 PM PDT 24
Peak memory 226484 kb
Host smart-7f3558f6-627a-4c79-ae06-d8d607e8b0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841634389 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.3841634389 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/6.kmac_lc_escalation/latest

Test location /workspace/coverage/default/6.kmac_long_msg_and_output.1104744600
Short name T731
Test name
Test status
Simulation time 40390054067 ps
CPU time 1480.85 seconds
Started Jul 25 05:12:28 PM PDT 24
Finished Jul 25 05:37:09 PM PDT 24
Peak memory 337972 kb
Host smart-1ceeb0b4-36b7-4b96-bac1-fd4963c978b8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104744600 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_an
d_output.1104744600 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/6.kmac_mubi.4144413239
Short name T663
Test name
Test status
Simulation time 4422767521 ps
CPU time 342.11 seconds
Started Jul 25 05:12:41 PM PDT 24
Finished Jul 25 05:18:23 PM PDT 24
Peak memory 249968 kb
Host smart-4c0e30df-ced2-48d6-938d-757195613267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144413239 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.4144413239 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_mubi/latest

Test location /workspace/coverage/default/6.kmac_sideload.3372083587
Short name T827
Test name
Test status
Simulation time 70837835669 ps
CPU time 395.83 seconds
Started Jul 25 05:12:28 PM PDT 24
Finished Jul 25 05:19:05 PM PDT 24
Peak memory 249432 kb
Host smart-e5e2615b-ff26-4de2-b147-af48becb6321
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372083587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.3372083587 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_sideload/latest

Test location /workspace/coverage/default/6.kmac_smoke.3684810961
Short name T459
Test name
Test status
Simulation time 597868454 ps
CPU time 19.42 seconds
Started Jul 25 05:12:28 PM PDT 24
Finished Jul 25 05:12:47 PM PDT 24
Peak memory 224860 kb
Host smart-65a1387e-1c3c-44c0-9d18-eee12fb89f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684810961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.3684810961 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_smoke/latest

Test location /workspace/coverage/default/6.kmac_stress_all.3455076578
Short name T718
Test name
Test status
Simulation time 49893014948 ps
CPU time 1308.34 seconds
Started Jul 25 05:12:33 PM PDT 24
Finished Jul 25 05:34:22 PM PDT 24
Peak memory 373328 kb
Host smart-776cfee8-2a05-43be-92ad-2bf8597aa1c6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3455076578 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.3455076578 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_stress_all/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_kmac.1075468994
Short name T355
Test name
Test status
Simulation time 423372239 ps
CPU time 5.06 seconds
Started Jul 25 05:12:48 PM PDT 24
Finished Jul 25 05:12:54 PM PDT 24
Peak memory 219472 kb
Host smart-a86a1976-2fd3-43f4-a645-1371d24f90be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075468994 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.kmac_test_vectors_kmac.1075468994 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_kmac_xof.3310931043
Short name T1047
Test name
Test status
Simulation time 899318536 ps
CPU time 6.58 seconds
Started Jul 25 05:12:35 PM PDT 24
Finished Jul 25 05:12:41 PM PDT 24
Peak memory 219476 kb
Host smart-edfb4878-37b1-449c-8f46-804cab0b651c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310931043 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.kmac_test_vectors_kmac_xof.3310931043 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_224.737015494
Short name T146
Test name
Test status
Simulation time 81197684849 ps
CPU time 1980.41 seconds
Started Jul 25 05:12:42 PM PDT 24
Finished Jul 25 05:45:42 PM PDT 24
Peak memory 398412 kb
Host smart-872e938d-43f2-4e99-b2f6-3fcb18b66c9b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=737015494 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_224.737015494 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_256.1625569290
Short name T245
Test name
Test status
Simulation time 131481929756 ps
CPU time 2018.98 seconds
Started Jul 25 05:12:39 PM PDT 24
Finished Jul 25 05:46:18 PM PDT 24
Peak memory 387816 kb
Host smart-38cd9359-a644-43fe-a8f2-8011927458c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1625569290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_256.1625569290 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_384.33931880
Short name T935
Test name
Test status
Simulation time 47948288409 ps
CPU time 1692.79 seconds
Started Jul 25 05:12:43 PM PDT 24
Finished Jul 25 05:40:56 PM PDT 24
Peak memory 342488 kb
Host smart-f59b3122-88bd-4c4c-8252-499ceb3bd127
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=33931880 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_384.33931880 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_shake_128.1671526022
Short name T500
Test name
Test status
Simulation time 241542903583 ps
CPU time 4605.78 seconds
Started Jul 25 05:12:40 PM PDT 24
Finished Jul 25 06:29:26 PM PDT 24
Peak memory 656252 kb
Host smart-41ca43d5-41fe-49fd-abef-c22c2d83b727
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1671526022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_128.1671526022 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_shake_256.3205270751
Short name T612
Test name
Test status
Simulation time 56712374548 ps
CPU time 4307.12 seconds
Started Jul 25 05:12:34 PM PDT 24
Finished Jul 25 06:24:22 PM PDT 24
Peak memory 567744 kb
Host smart-5445361a-d453-490c-8a0d-da29c2c69928
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3205270751 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_256.3205270751 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/7.kmac_alert_test.3905820169
Short name T852
Test name
Test status
Simulation time 53994831 ps
CPU time 0.81 seconds
Started Jul 25 05:12:37 PM PDT 24
Finished Jul 25 05:12:38 PM PDT 24
Peak memory 218304 kb
Host smart-8d260eb7-2647-48c3-8131-782fc5b35be3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905820169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.3905820169 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_alert_test/latest

Test location /workspace/coverage/default/7.kmac_app.1747700744
Short name T259
Test name
Test status
Simulation time 5169793774 ps
CPU time 100.12 seconds
Started Jul 25 05:12:41 PM PDT 24
Finished Jul 25 05:14:21 PM PDT 24
Peak memory 234548 kb
Host smart-622158a6-f634-487f-8107-21f1a0560584
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747700744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.1747700744 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/7.kmac_app/latest

Test location /workspace/coverage/default/7.kmac_burst_write.1898521897
Short name T1027
Test name
Test status
Simulation time 76438011718 ps
CPU time 947.03 seconds
Started Jul 25 05:12:31 PM PDT 24
Finished Jul 25 05:28:19 PM PDT 24
Peak memory 243028 kb
Host smart-4cd302a2-7f57-468b-975d-637c534f0fd1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898521897 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.1898521897
+enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_burst_write/latest

Test location /workspace/coverage/default/7.kmac_edn_timeout_error.2730426695
Short name T700
Test name
Test status
Simulation time 35797573 ps
CPU time 1.4 seconds
Started Jul 25 05:12:35 PM PDT 24
Finished Jul 25 05:12:36 PM PDT 24
Peak memory 218336 kb
Host smart-337f01ec-e870-4e6a-a890-10bb9c41f2e2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2730426695 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.2730426695 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_mode_error.237896977
Short name T86
Test name
Test status
Simulation time 14531674 ps
CPU time 0.96 seconds
Started Jul 25 05:12:39 PM PDT 24
Finished Jul 25 05:12:40 PM PDT 24
Peak memory 220344 kb
Host smart-93d89128-2d05-475f-ab89-0fe3cee4a24d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=237896977 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.237896977 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_ready_error.3296313478
Short name T752
Test name
Test status
Simulation time 10779986443 ps
CPU time 31.47 seconds
Started Jul 25 05:12:35 PM PDT 24
Finished Jul 25 05:13:07 PM PDT 24
Peak memory 218604 kb
Host smart-0e413fb5-9be9-4d7b-a43c-6be7b0547a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296313478 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.3296313478 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_refresh.3942051806
Short name T683
Test name
Test status
Simulation time 3099987021 ps
CPU time 20.24 seconds
Started Jul 25 05:12:41 PM PDT 24
Finished Jul 25 05:13:01 PM PDT 24
Peak memory 225100 kb
Host smart-7b827c96-2e43-4e1f-8140-c693693fb9a6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942051806 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.39
42051806 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/7.kmac_error.1459471516
Short name T693
Test name
Test status
Simulation time 6488498512 ps
CPU time 177.69 seconds
Started Jul 25 05:12:42 PM PDT 24
Finished Jul 25 05:15:40 PM PDT 24
Peak memory 256456 kb
Host smart-641185ed-535b-40bd-a0d8-c315ab1ecd34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459471516 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.1459471516 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_error/latest

Test location /workspace/coverage/default/7.kmac_key_error.3408780562
Short name T1001
Test name
Test status
Simulation time 156297401 ps
CPU time 1.53 seconds
Started Jul 25 05:12:42 PM PDT 24
Finished Jul 25 05:12:44 PM PDT 24
Peak memory 222208 kb
Host smart-0e3920b8-f7a8-4e45-af68-a34c3b39b67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408780562 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.3408780562 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_key_error/latest

Test location /workspace/coverage/default/7.kmac_lc_escalation.1624222202
Short name T486
Test name
Test status
Simulation time 80445080 ps
CPU time 1.38 seconds
Started Jul 25 05:12:33 PM PDT 24
Finished Jul 25 05:12:35 PM PDT 24
Peak memory 226604 kb
Host smart-3dabf69b-715b-4997-9076-cc0999873933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624222202 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.1624222202 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/7.kmac_lc_escalation/latest

Test location /workspace/coverage/default/7.kmac_long_msg_and_output.2172754038
Short name T987
Test name
Test status
Simulation time 27608499734 ps
CPU time 755.36 seconds
Started Jul 25 05:12:36 PM PDT 24
Finished Jul 25 05:25:11 PM PDT 24
Peak memory 274824 kb
Host smart-81db0f12-0672-4de0-bfc7-ec14eca6c6a0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172754038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_an
d_output.2172754038 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/7.kmac_mubi.2271753443
Short name T62
Test name
Test status
Simulation time 9800600382 ps
CPU time 307.17 seconds
Started Jul 25 05:12:43 PM PDT 24
Finished Jul 25 05:17:50 PM PDT 24
Peak memory 248072 kb
Host smart-d5a94f41-990b-4e8e-892f-7919b8521d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271753443 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.2271753443 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_mubi/latest

Test location /workspace/coverage/default/7.kmac_sideload.1938621897
Short name T312
Test name
Test status
Simulation time 22551508222 ps
CPU time 454.91 seconds
Started Jul 25 05:12:41 PM PDT 24
Finished Jul 25 05:20:16 PM PDT 24
Peak memory 257292 kb
Host smart-7035fd8e-75f0-44b7-b22e-982c31dd8784
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938621897 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.1938621897 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_sideload/latest

Test location /workspace/coverage/default/7.kmac_smoke.542221508
Short name T834
Test name
Test status
Simulation time 2239987731 ps
CPU time 27.74 seconds
Started Jul 25 05:12:36 PM PDT 24
Finished Jul 25 05:13:04 PM PDT 24
Peak memory 224768 kb
Host smart-0af77ce7-b723-41db-88a5-c10f25caac62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542221508 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.542221508 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_smoke/latest

Test location /workspace/coverage/default/7.kmac_stress_all.812661414
Short name T17
Test name
Test status
Simulation time 45295938515 ps
CPU time 792.27 seconds
Started Jul 25 05:12:52 PM PDT 24
Finished Jul 25 05:26:05 PM PDT 24
Peak memory 315644 kb
Host smart-d91c9c5e-942c-405c-b27e-2a8f14fc0bbd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=812661414 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.812661414 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_stress_all/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_kmac.3112288102
Short name T932
Test name
Test status
Simulation time 2963911494 ps
CPU time 5.97 seconds
Started Jul 25 05:12:41 PM PDT 24
Finished Jul 25 05:12:47 PM PDT 24
Peak memory 218676 kb
Host smart-c46739e6-f4f7-4ec1-9744-c64fe5549414
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112288102 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.kmac_test_vectors_kmac.3112288102 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_kmac_xof.3068871851
Short name T837
Test name
Test status
Simulation time 213873301 ps
CPU time 5.7 seconds
Started Jul 25 05:12:38 PM PDT 24
Finished Jul 25 05:12:44 PM PDT 24
Peak memory 218628 kb
Host smart-bc56a276-e6a4-4bb0-adf3-3c9440345524
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068871851 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.kmac_test_vectors_kmac_xof.3068871851 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_224.2853848262
Short name T317
Test name
Test status
Simulation time 81670928212 ps
CPU time 2158.96 seconds
Started Jul 25 05:12:43 PM PDT 24
Finished Jul 25 05:48:43 PM PDT 24
Peak memory 397280 kb
Host smart-eb874e89-dbe6-4ba1-aacb-2cda34b53529
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2853848262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_224.2853848262 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_256.147785860
Short name T896
Test name
Test status
Simulation time 46495217016 ps
CPU time 1859.39 seconds
Started Jul 25 05:12:32 PM PDT 24
Finished Jul 25 05:43:32 PM PDT 24
Peak memory 381656 kb
Host smart-13ef478c-8555-4e2a-98cb-ed27f063f299
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=147785860 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_256.147785860 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_384.869051043
Short name T314
Test name
Test status
Simulation time 69761032176 ps
CPU time 1754.63 seconds
Started Jul 25 05:12:41 PM PDT 24
Finished Jul 25 05:41:56 PM PDT 24
Peak memory 338360 kb
Host smart-22ac3a4b-a0a9-44fb-8a8a-9dc6d5516eab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=869051043 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_384.869051043 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_512.2706725171
Short name T1035
Test name
Test status
Simulation time 42099180190 ps
CPU time 1162.8 seconds
Started Jul 25 05:12:38 PM PDT 24
Finished Jul 25 05:32:01 PM PDT 24
Peak memory 301184 kb
Host smart-7ffe6ca8-775b-4214-abe1-5d09f8f56354
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2706725171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_512.2706725171 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_shake_128.75792959
Short name T959
Test name
Test status
Simulation time 1035150033359 ps
CPU time 5887.91 seconds
Started Jul 25 05:12:42 PM PDT 24
Finished Jul 25 06:50:51 PM PDT 24
Peak memory 658496 kb
Host smart-0ec31ec8-9ce2-4870-812d-8a23f940fdcf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=75792959 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_128.75792959 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_shake_256.2630816594
Short name T492
Test name
Test status
Simulation time 628878044475 ps
CPU time 4864.09 seconds
Started Jul 25 05:12:41 PM PDT 24
Finished Jul 25 06:33:46 PM PDT 24
Peak memory 567412 kb
Host smart-c168b661-cec2-42c2-b81e-f75e6e538bb0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2630816594 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_256.2630816594 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/8.kmac_alert_test.3233845336
Short name T498
Test name
Test status
Simulation time 54930693 ps
CPU time 0.88 seconds
Started Jul 25 05:12:54 PM PDT 24
Finished Jul 25 05:12:55 PM PDT 24
Peak memory 218292 kb
Host smart-4b490685-66b3-4ced-9075-72342ccea6ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233845336 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.3233845336 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_alert_test/latest

Test location /workspace/coverage/default/8.kmac_app.723807233
Short name T298
Test name
Test status
Simulation time 15506152408 ps
CPU time 381.76 seconds
Started Jul 25 05:12:43 PM PDT 24
Finished Jul 25 05:19:05 PM PDT 24
Peak memory 252740 kb
Host smart-8f146674-d052-49c5-b325-fa2905626dad
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723807233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.723807233 +enable_masking=1
+sw_key_masked=0
Directory /workspace/8.kmac_app/latest

Test location /workspace/coverage/default/8.kmac_app_with_partial_data.2313972300
Short name T988
Test name
Test status
Simulation time 68005762082 ps
CPU time 384.74 seconds
Started Jul 25 05:12:39 PM PDT 24
Finished Jul 25 05:19:04 PM PDT 24
Peak memory 253176 kb
Host smart-50d1799c-0a4d-409b-a770-85d82c1a92c0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313972300 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_par
tial_data.2313972300 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/8.kmac_burst_write.597670993
Short name T300
Test name
Test status
Simulation time 307867709190 ps
CPU time 1389.31 seconds
Started Jul 25 05:12:43 PM PDT 24
Finished Jul 25 05:35:53 PM PDT 24
Peak memory 238580 kb
Host smart-be9651d6-8835-49c3-b1dc-9f6c0f0e18bd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597670993 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.597670993 +
enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_burst_write/latest

Test location /workspace/coverage/default/8.kmac_edn_timeout_error.3026436128
Short name T664
Test name
Test status
Simulation time 64864589 ps
CPU time 0.83 seconds
Started Jul 25 05:12:54 PM PDT 24
Finished Jul 25 05:12:54 PM PDT 24
Peak memory 218284 kb
Host smart-f026cea0-a85b-4508-9927-c0f8898ad1a3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3026436128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.3026436128 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_mode_error.2660570958
Short name T889
Test name
Test status
Simulation time 147450672 ps
CPU time 1.42 seconds
Started Jul 25 05:12:51 PM PDT 24
Finished Jul 25 05:12:52 PM PDT 24
Peak memory 222328 kb
Host smart-b08f70bd-dd9b-466f-b81a-2de6bdb90551
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2660570958 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.2660570958 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_ready_error.2048938812
Short name T1065
Test name
Test status
Simulation time 954812592 ps
CPU time 11.15 seconds
Started Jul 25 05:12:51 PM PDT 24
Finished Jul 25 05:13:02 PM PDT 24
Peak memory 218524 kb
Host smart-12f26152-a857-4d56-a8e4-0ce3eab8a301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048938812 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.2048938812 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_refresh.1273265290
Short name T1075
Test name
Test status
Simulation time 10272879078 ps
CPU time 307.95 seconds
Started Jul 25 05:12:39 PM PDT 24
Finished Jul 25 05:17:47 PM PDT 24
Peak memory 249836 kb
Host smart-1723a484-0675-433d-a89e-0a9ebb11277c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273265290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.12
73265290 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/8.kmac_error.3528711035
Short name T579
Test name
Test status
Simulation time 5558009790 ps
CPU time 173.4 seconds
Started Jul 25 05:12:51 PM PDT 24
Finished Jul 25 05:15:45 PM PDT 24
Peak memory 251256 kb
Host smart-601939d7-d62a-4466-bb87-3a1d6b524466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528711035 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.3528711035 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_error/latest

Test location /workspace/coverage/default/8.kmac_key_error.3598816940
Short name T680
Test name
Test status
Simulation time 1900045861 ps
CPU time 12.46 seconds
Started Jul 25 05:12:48 PM PDT 24
Finished Jul 25 05:13:01 PM PDT 24
Peak memory 225740 kb
Host smart-0afcfae1-1875-4704-8987-184cb361e2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598816940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.3598816940 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_key_error/latest

Test location /workspace/coverage/default/8.kmac_lc_escalation.2882985135
Short name T926
Test name
Test status
Simulation time 81734028 ps
CPU time 1.36 seconds
Started Jul 25 05:12:48 PM PDT 24
Finished Jul 25 05:12:49 PM PDT 24
Peak memory 226560 kb
Host smart-68b34b91-b69a-426d-b9a6-f21fdbeaaff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882985135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.2882985135 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/8.kmac_lc_escalation/latest

Test location /workspace/coverage/default/8.kmac_long_msg_and_output.3007875111
Short name T412
Test name
Test status
Simulation time 10738892175 ps
CPU time 557.47 seconds
Started Jul 25 05:12:42 PM PDT 24
Finished Jul 25 05:22:00 PM PDT 24
Peak memory 270132 kb
Host smart-9eff3c42-4ea9-4931-8e58-64e1d952e65f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007875111 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_an
d_output.3007875111 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/8.kmac_mubi.2726979931
Short name T60
Test name
Test status
Simulation time 4008055642 ps
CPU time 62.75 seconds
Started Jul 25 05:12:52 PM PDT 24
Finished Jul 25 05:13:55 PM PDT 24
Peak memory 229760 kb
Host smart-26a2fce0-a2fd-468a-8d2b-05037279bf03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726979931 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.2726979931 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_mubi/latest

Test location /workspace/coverage/default/8.kmac_sideload.2973162922
Short name T241
Test name
Test status
Simulation time 1533380704 ps
CPU time 137.82 seconds
Started Jul 25 05:13:24 PM PDT 24
Finished Jul 25 05:15:42 PM PDT 24
Peak memory 235844 kb
Host smart-19595d01-8ae7-4ab9-b33a-e20e3b201f5c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973162922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.2973162922 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_sideload/latest

Test location /workspace/coverage/default/8.kmac_smoke.2049704545
Short name T623
Test name
Test status
Simulation time 2848634383 ps
CPU time 20.08 seconds
Started Jul 25 05:12:43 PM PDT 24
Finished Jul 25 05:13:03 PM PDT 24
Peak memory 226676 kb
Host smart-789cab1f-002b-4f16-a2c3-e9f3fbf4d9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049704545 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.2049704545 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_smoke/latest

Test location /workspace/coverage/default/8.kmac_stress_all.2133000502
Short name T405
Test name
Test status
Simulation time 29748774991 ps
CPU time 582.9 seconds
Started Jul 25 05:12:47 PM PDT 24
Finished Jul 25 05:22:30 PM PDT 24
Peak memory 269544 kb
Host smart-26d65c40-a8be-42ef-90a7-8852c23d9615
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2133000502 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.2133000502 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_stress_all/latest

Test location /workspace/coverage/default/8.kmac_stress_all_with_rand_reset.2809212622
Short name T49
Test name
Test status
Simulation time 62168372833 ps
CPU time 1682.86 seconds
Started Jul 25 05:12:45 PM PDT 24
Finished Jul 25 05:40:48 PM PDT 24
Peak memory 326216 kb
Host smart-235dc2d5-7a00-4a05-a771-de27ad4e55c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2809212622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all_with_rand_reset.2809212622 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_kmac.8894296
Short name T494
Test name
Test status
Simulation time 1068598420 ps
CPU time 6.73 seconds
Started Jul 25 05:12:41 PM PDT 24
Finished Jul 25 05:12:48 PM PDT 24
Peak memory 218520 kb
Host smart-940fd8bf-665f-4a05-bc48-af2c0fcd7c59
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8894296 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.kmac_test_vectors_kmac.8894296 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_kmac_xof.1328034076
Short name T746
Test name
Test status
Simulation time 783593924 ps
CPU time 5.76 seconds
Started Jul 25 05:12:43 PM PDT 24
Finished Jul 25 05:12:49 PM PDT 24
Peak memory 218552 kb
Host smart-06ca8232-0668-457d-8133-c2dc74857d56
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328034076 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.kmac_test_vectors_kmac_xof.1328034076 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_224.4210077519
Short name T618
Test name
Test status
Simulation time 36099162999 ps
CPU time 2092.14 seconds
Started Jul 25 05:12:42 PM PDT 24
Finished Jul 25 05:47:35 PM PDT 24
Peak memory 400828 kb
Host smart-0fea3a25-ef82-4e79-bda3-5e61c50f5a33
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4210077519 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_224.4210077519 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_256.166863029
Short name T923
Test name
Test status
Simulation time 245858254604 ps
CPU time 2286.26 seconds
Started Jul 25 05:12:37 PM PDT 24
Finished Jul 25 05:50:43 PM PDT 24
Peak memory 384880 kb
Host smart-58177abd-6d63-47c2-a3a5-c27467c0e683
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=166863029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_256.166863029 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_384.2889514910
Short name T1061
Test name
Test status
Simulation time 29069045626 ps
CPU time 1385.87 seconds
Started Jul 25 05:12:42 PM PDT 24
Finished Jul 25 05:35:48 PM PDT 24
Peak memory 339224 kb
Host smart-d2bde6a9-6a9d-40c4-a39c-c35aeb4eec66
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2889514910 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_384.2889514910 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_512.1390727567
Short name T580
Test name
Test status
Simulation time 45650076240 ps
CPU time 1316 seconds
Started Jul 25 05:12:43 PM PDT 24
Finished Jul 25 05:34:39 PM PDT 24
Peak memory 306016 kb
Host smart-e3aee149-fd79-430e-92d6-7bf2ee03bd7d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1390727567 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_512.1390727567 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_shake_128.3133734432
Short name T1020
Test name
Test status
Simulation time 253908489184 ps
CPU time 5322.15 seconds
Started Jul 25 05:12:43 PM PDT 24
Finished Jul 25 06:41:26 PM PDT 24
Peak memory 667112 kb
Host smart-9f823efa-2405-4a33-95df-78145c4cde8d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3133734432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_128.3133734432 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_shake_256.3461526147
Short name T236
Test name
Test status
Simulation time 63739847336 ps
CPU time 4271.85 seconds
Started Jul 25 05:12:42 PM PDT 24
Finished Jul 25 06:23:54 PM PDT 24
Peak memory 566916 kb
Host smart-8f54fa63-adb7-455b-a6f6-aa7f64dc77d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3461526147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_256.3461526147 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/9.kmac_alert_test.2194313513
Short name T415
Test name
Test status
Simulation time 14463575 ps
CPU time 0.81 seconds
Started Jul 25 05:12:51 PM PDT 24
Finished Jul 25 05:12:52 PM PDT 24
Peak memory 218292 kb
Host smart-e87bed6f-de36-4f9b-ad32-5d8b831a90bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194313513 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.2194313513 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_alert_test/latest

Test location /workspace/coverage/default/9.kmac_app.3082144705
Short name T724
Test name
Test status
Simulation time 10096560461 ps
CPU time 352.82 seconds
Started Jul 25 05:12:48 PM PDT 24
Finished Jul 25 05:18:41 PM PDT 24
Peak memory 251348 kb
Host smart-9a1ae9c7-fcec-45aa-bed7-6d7fff4558bd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082144705 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.3082144705 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/9.kmac_app/latest

Test location /workspace/coverage/default/9.kmac_app_with_partial_data.3278175163
Short name T902
Test name
Test status
Simulation time 2611945218 ps
CPU time 112.08 seconds
Started Jul 25 05:12:53 PM PDT 24
Finished Jul 25 05:14:45 PM PDT 24
Peak memory 234360 kb
Host smart-c7707bf0-35f4-48cf-b3a3-361f46346417
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278175163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_par
tial_data.3278175163 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/9.kmac_burst_write.620744828
Short name T891
Test name
Test status
Simulation time 140551092897 ps
CPU time 735.24 seconds
Started Jul 25 05:12:50 PM PDT 24
Finished Jul 25 05:25:05 PM PDT 24
Peak memory 236156 kb
Host smart-5c6d196c-c3a0-42b9-aa8e-695faabe2d95
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620744828 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.620744828 +
enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_burst_write/latest

Test location /workspace/coverage/default/9.kmac_edn_timeout_error.2693264659
Short name T560
Test name
Test status
Simulation time 2435169839 ps
CPU time 28.9 seconds
Started Jul 25 05:12:45 PM PDT 24
Finished Jul 25 05:13:14 PM PDT 24
Peak memory 226792 kb
Host smart-a9aeafc6-3043-4f7b-85b4-820b6d351834
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2693264659 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.2693264659 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_mode_error.129795376
Short name T517
Test name
Test status
Simulation time 121730515 ps
CPU time 1.16 seconds
Started Jul 25 05:12:47 PM PDT 24
Finished Jul 25 05:12:48 PM PDT 24
Peak memory 222028 kb
Host smart-1d302e4c-36ea-4e9d-aab6-c01f161bf592
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=129795376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.129795376 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_ready_error.275483009
Short name T854
Test name
Test status
Simulation time 25331958913 ps
CPU time 69.19 seconds
Started Jul 25 05:12:47 PM PDT 24
Finished Jul 25 05:13:57 PM PDT 24
Peak memory 220132 kb
Host smart-00b5977d-58ac-4210-9f70-c7122696337f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275483009 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.275483009 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_refresh.2696394333
Short name T737
Test name
Test status
Simulation time 7422157899 ps
CPU time 177.83 seconds
Started Jul 25 05:12:45 PM PDT 24
Finished Jul 25 05:15:43 PM PDT 24
Peak memory 241684 kb
Host smart-82eaffca-4245-44f6-94ca-7c461604817b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696394333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.26
96394333 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/9.kmac_error.2887103149
Short name T28
Test name
Test status
Simulation time 5779082808 ps
CPU time 478.3 seconds
Started Jul 25 05:12:47 PM PDT 24
Finished Jul 25 05:20:45 PM PDT 24
Peak memory 269368 kb
Host smart-7385170a-dfb6-42c1-8c62-811395f3daa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887103149 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.2887103149 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_error/latest

Test location /workspace/coverage/default/9.kmac_key_error.2528351460
Short name T1049
Test name
Test status
Simulation time 3139995284 ps
CPU time 8.45 seconds
Started Jul 25 05:12:44 PM PDT 24
Finished Jul 25 05:12:53 PM PDT 24
Peak memory 225348 kb
Host smart-60f5f702-3f5e-4283-8aee-fd0a48b66ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528351460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.2528351460 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_key_error/latest

Test location /workspace/coverage/default/9.kmac_long_msg_and_output.186175332
Short name T1056
Test name
Test status
Simulation time 103751926253 ps
CPU time 2640.13 seconds
Started Jul 25 05:12:51 PM PDT 24
Finished Jul 25 05:56:51 PM PDT 24
Peak memory 455804 kb
Host smart-fb06c62f-6523-490e-bc35-019ddd5b6784
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186175332 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_and
_output.186175332 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/9.kmac_mubi.2910526169
Short name T820
Test name
Test status
Simulation time 3293809137 ps
CPU time 6.22 seconds
Started Jul 25 05:12:51 PM PDT 24
Finished Jul 25 05:12:57 PM PDT 24
Peak memory 224512 kb
Host smart-1d91787a-500c-4bfd-8f92-f68b3c1cfb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910526169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.2910526169 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_mubi/latest

Test location /workspace/coverage/default/9.kmac_sideload.2981684965
Short name T1016
Test name
Test status
Simulation time 33395083118 ps
CPU time 335.9 seconds
Started Jul 25 05:12:52 PM PDT 24
Finished Jul 25 05:18:28 PM PDT 24
Peak memory 248548 kb
Host smart-b848abc0-5a81-4916-afa8-3e2a597b805c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981684965 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.2981684965 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_sideload/latest

Test location /workspace/coverage/default/9.kmac_smoke.3190225510
Short name T846
Test name
Test status
Simulation time 1266536655 ps
CPU time 46.12 seconds
Started Jul 25 05:12:48 PM PDT 24
Finished Jul 25 05:13:34 PM PDT 24
Peak memory 226576 kb
Host smart-b864b3f4-1305-49b2-992d-e9c2fefc052c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190225510 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.3190225510 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_smoke/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_kmac.3642773168
Short name T505
Test name
Test status
Simulation time 399211514 ps
CPU time 5.47 seconds
Started Jul 25 05:12:56 PM PDT 24
Finished Jul 25 05:13:02 PM PDT 24
Peak memory 219384 kb
Host smart-1edf7c47-6450-4474-8c4b-f638b4bad34b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642773168 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.kmac_test_vectors_kmac.3642773168 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_kmac_xof.2253900096
Short name T575
Test name
Test status
Simulation time 474731551 ps
CPU time 6.78 seconds
Started Jul 25 05:12:47 PM PDT 24
Finished Jul 25 05:12:53 PM PDT 24
Peak memory 218620 kb
Host smart-b6fb68bd-7e44-4bd9-b567-701c5d21bbd5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253900096 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.kmac_test_vectors_kmac_xof.2253900096 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_224.845064959
Short name T646
Test name
Test status
Simulation time 21149173850 ps
CPU time 1973.06 seconds
Started Jul 25 05:12:49 PM PDT 24
Finished Jul 25 05:45:42 PM PDT 24
Peak memory 391780 kb
Host smart-b0ec769d-4b84-44a4-ba74-753e49a864d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=845064959 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_224.845064959 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_256.254798030
Short name T703
Test name
Test status
Simulation time 171687778949 ps
CPU time 2071.71 seconds
Started Jul 25 05:12:47 PM PDT 24
Finished Jul 25 05:47:19 PM PDT 24
Peak memory 391384 kb
Host smart-bd2e27fe-2b42-4a91-829e-cfe11864df55
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=254798030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_256.254798030 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_384.3718909923
Short name T721
Test name
Test status
Simulation time 97093350452 ps
CPU time 1595.5 seconds
Started Jul 25 05:12:45 PM PDT 24
Finished Jul 25 05:39:20 PM PDT 24
Peak memory 340536 kb
Host smart-511c6951-bcb0-462a-b899-bb0611ef1be5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3718909923 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_384.3718909923 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_512.3316644753
Short name T205
Test name
Test status
Simulation time 13097512873 ps
CPU time 1029.92 seconds
Started Jul 25 05:12:53 PM PDT 24
Finished Jul 25 05:30:03 PM PDT 24
Peak memory 296432 kb
Host smart-cc254bff-bd07-4e59-b217-c119144e319a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3316644753 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_512.3316644753 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_shake_128.614851934
Short name T697
Test name
Test status
Simulation time 528680499955 ps
CPU time 6089.73 seconds
Started Jul 25 05:12:44 PM PDT 24
Finished Jul 25 06:54:14 PM PDT 24
Peak memory 666996 kb
Host smart-46e5c9dc-72f6-4d6f-8214-ad4ad1db8948
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=614851934 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_128.614851934 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_shake_256.3778892325
Short name T866
Test name
Test status
Simulation time 257472508808 ps
CPU time 5019.43 seconds
Started Jul 25 05:12:46 PM PDT 24
Finished Jul 25 06:36:26 PM PDT 24
Peak memory 567312 kb
Host smart-c9788744-e2a6-4571-acd6-a266951c29ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3778892325 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_256.3778892325 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_shake_256/latest
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