Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	98902837	1			T1	28617		T2	219594		T3	2974
all_values[1]	98902837	1			T1	28617		T2	219594		T3	2974
all_values[2]	98902837	1			T1	28617		T2	219594		T3	2974

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

451430

1

T2

3

T3

2

T31

12

auto[1]

296257081

1

T1

85851

T2

658779

T3

8920

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

295195695

1

T1

85116

T2

657024

T3

8838

auto[1]

1512816

1

T1

735

T2

1758

T3

84

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	172969	1			T31	8		T32	13		T34	52
all_values[0]	auto[0]	auto[1]	1983	1			T31	4		T32	10		T34	10
all_values[0]	auto[1]	auto[0]	98225596	1			T1	28372		T2	219008		T3	2946
all_values[0]	auto[1]	auto[1]	502289	1			T1	245		T2	586		T3	28
all_values[1]	auto[0]	auto[0]	136219	1			T2	2		T34	13		T18	625
all_values[1]	auto[0]	auto[1]	1565	1			T2	1		T34	4		T18	6
all_values[1]	auto[1]	auto[0]	98262346	1			T1	28372		T2	219006		T3	2946
all_values[1]	auto[1]	auto[1]	502707	1			T1	245		T2	585		T3	28
all_values[2]	auto[0]	auto[0]	137204	1			T3	2		T32	3		T55	5
all_values[2]	auto[0]	auto[1]	1490	1			T32	4		T55	2		T18	2
all_values[2]	auto[1]	auto[0]	98261361	1			T1	28372		T2	219008		T3	2944
all_values[2]	auto[1]	auto[1]	502782	1			T1	245		T2	586		T3	28