Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
333557 |
1 |
|
|
T1 |
368 |
|
T2 |
2 |
|
T3 |
64 |
auto[1] |
351944 |
1 |
|
|
T2 |
778 |
|
T31 |
16 |
|
T7 |
320 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
172029 |
1 |
|
|
T1 |
98 |
|
T2 |
177 |
|
T3 |
16 |
lower_val |
170132 |
1 |
|
|
T1 |
102 |
|
T2 |
212 |
|
T3 |
20 |
zero_val |
1775 |
1 |
|
|
T1 |
1 |
|
T2 |
3 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
254208 |
1 |
|
|
T1 |
184 |
|
T2 |
178 |
|
T3 |
38 |
lower_val |
254931 |
1 |
|
|
T1 |
184 |
|
T2 |
182 |
|
T3 |
26 |
zero_val |
176362 |
1 |
|
|
T2 |
420 |
|
T31 |
8 |
|
T7 |
172 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
41760 |
1 |
|
|
T1 |
55 |
|
T3 |
8 |
|
T32 |
573 |
higher_val |
higher_val |
auto[1] |
21827 |
1 |
|
|
T2 |
38 |
|
T31 |
1 |
|
T7 |
20 |
higher_val |
lower_val |
auto[0] |
41810 |
1 |
|
|
T1 |
43 |
|
T3 |
8 |
|
T32 |
575 |
higher_val |
lower_val |
auto[1] |
22285 |
1 |
|
|
T2 |
41 |
|
T7 |
13 |
|
T55 |
32 |
higher_val |
zero_val |
auto[0] |
56 |
1 |
|
|
T7 |
1 |
|
T35 |
1 |
|
T14 |
1 |
higher_val |
zero_val |
auto[1] |
44291 |
1 |
|
|
T2 |
98 |
|
T31 |
1 |
|
T7 |
37 |
lower_val |
higher_val |
auto[0] |
41009 |
1 |
|
|
T1 |
46 |
|
T2 |
1 |
|
T3 |
12 |
lower_val |
higher_val |
auto[1] |
21900 |
1 |
|
|
T2 |
50 |
|
T7 |
23 |
|
T55 |
45 |
lower_val |
lower_val |
auto[0] |
41173 |
1 |
|
|
T1 |
56 |
|
T3 |
8 |
|
T32 |
596 |
lower_val |
lower_val |
auto[1] |
22026 |
1 |
|
|
T2 |
49 |
|
T31 |
2 |
|
T7 |
19 |
lower_val |
zero_val |
auto[0] |
102 |
1 |
|
|
T47 |
1 |
|
T72 |
1 |
|
T17 |
1 |
lower_val |
zero_val |
auto[1] |
43922 |
1 |
|
|
T2 |
112 |
|
T31 |
3 |
|
T7 |
52 |
zero_val |
higher_val |
auto[0] |
552 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T34 |
1 |
zero_val |
higher_val |
auto[1] |
122 |
1 |
|
|
T72 |
4 |
|
T191 |
1 |
|
T14 |
2 |
zero_val |
lower_val |
auto[0] |
557 |
1 |
|
|
T1 |
1 |
|
T31 |
1 |
|
T32 |
3 |
zero_val |
lower_val |
auto[1] |
134 |
1 |
|
|
T2 |
1 |
|
T35 |
1 |
|
T72 |
1 |
zero_val |
zero_val |
auto[0] |
228 |
1 |
|
|
T7 |
1 |
|
T18 |
1 |
|
T35 |
1 |
zero_val |
zero_val |
auto[1] |
182 |
1 |
|
|
T2 |
1 |
|
T35 |
1 |
|
T72 |
3 |