Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	10264	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	8870	1			T2	17		T32	30		T55	24
len_5001_7500	14310	1			T2	17		T32	30		T55	24
len_2501_5000	9226	1			T2	17		T32	30		T55	24
len_1025_2500	5365	1			T2	10		T32	16		T55	14
len_769_1024	5964	1			T1	48		T2	2		T3	4
len_513_768	6408	1			T1	45		T2	2		T3	5
len_257_512	20874	1			T1	39		T2	2		T3	8
len_0_256	254399	1			T1	32		T2	290		T3	2
len_keccak_block_sizes[72]	726	1			T2	2		T32	3		T55	2
len_keccak_block_sizes[104]	622	1			T1	1		T2	2		T32	3
len_keccak_block_sizes[136]	517	1			T2	2		T32	3		T38	2
len_keccak_block_sizes[144]	411	1			T2	2		T32	3		T38	2
len_keccak_block_sizes[168]	311	1			T32	3		T72	3		T192	3
len_1	760	1			T1	1		T2	2		T32	3
len_0	1202	1			T2	2		T32	3		T7	1