Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	98902837	1			T1	28617		T2	219594		T3	2974
all_pins[1]	98902837	1			T1	28617		T2	219594		T3	2974
all_pins[2]	98902837	1			T1	28617		T2	219594		T3	2974

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	295866441	1			T1	84453		T2	658196		T3	8894
values[0x1]	842070	1			T1	1398		T2	586		T3	28
transitions[0x0=>0x1]	839675	1			T1	1398		T2	586		T3	28
transitions[0x1=>0x0]	839703	1			T1	1398		T2	586		T3	28

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	98400548	1			T1	28372		T2	219008		T3	2946
all_pins[0]	values[0x1]	502289	1			T1	245		T2	586		T3	28
all_pins[0]	transitions[0x0=>0x1]	502277	1			T1	245		T2	586		T3	28
all_pins[0]	transitions[0x1=>0x0]	6316	1			T1	87		T7	37		T36	75
all_pins[1]	values[0x0]	98896509	1			T1	28530		T2	219594		T3	2974
all_pins[1]	values[0x1]	6328	1			T1	87		T7	37		T36	75
all_pins[1]	transitions[0x0=>0x1]	5982	1			T1	87		T7	37		T36	75
all_pins[1]	transitions[0x1=>0x0]	333107	1			T1	1066		T18	827		T19	424
all_pins[2]	values[0x0]	98569384	1			T1	27551		T2	219594		T3	2974
all_pins[2]	values[0x1]	333453	1			T1	1066		T18	827		T19	424
all_pins[2]	transitions[0x0=>0x1]	331416	1			T1	1066		T18	827		T19	424
all_pins[2]	transitions[0x1=>0x0]	500280	1			T1	245		T2	586		T3	28