Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10462141 |
1 |
|
|
T1 |
25757 |
|
T2 |
2730 |
|
T3 |
4227 |
auto[1] |
10462138 |
1 |
|
|
T1 |
25757 |
|
T2 |
2730 |
|
T3 |
4227 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
20690449 |
1 |
|
|
T1 |
51286 |
|
T2 |
5460 |
|
T3 |
8418 |
triple_byte_access |
77318 |
1 |
|
|
T1 |
88 |
|
T3 |
8 |
|
T32 |
558 |
halfword_access |
78672 |
1 |
|
|
T1 |
62 |
|
T3 |
10 |
|
T32 |
558 |
byte_access |
77840 |
1 |
|
|
T1 |
78 |
|
T3 |
18 |
|
T32 |
558 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10345226 |
1 |
|
|
T1 |
25643 |
|
T2 |
2730 |
|
T3 |
4209 |
auto[0] |
triple_byte_access |
38659 |
1 |
|
|
T1 |
44 |
|
T3 |
4 |
|
T32 |
279 |
auto[0] |
halfword_access |
39336 |
1 |
|
|
T1 |
31 |
|
T3 |
5 |
|
T32 |
279 |
auto[0] |
byte_access |
38920 |
1 |
|
|
T1 |
39 |
|
T3 |
9 |
|
T32 |
279 |
auto[1] |
word_access |
10345223 |
1 |
|
|
T1 |
25643 |
|
T2 |
2730 |
|
T3 |
4209 |
auto[1] |
triple_byte_access |
38659 |
1 |
|
|
T1 |
44 |
|
T3 |
4 |
|
T32 |
279 |
auto[1] |
halfword_access |
39336 |
1 |
|
|
T1 |
31 |
|
T3 |
5 |
|
T32 |
279 |
auto[1] |
byte_access |
38920 |
1 |
|
|
T1 |
39 |
|
T3 |
9 |
|
T32 |
279 |