Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	61407432	1			T1	161		T3	273		T18	160264
all_values[1]	61407432	1			T1	161		T3	273		T18	160264
all_values[2]	61407432	1			T1	161		T3	273		T18	160264

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

511779

1

T1

75

T3

12

T18

6

auto[1]

183710517

1

T1

408

T3

807

T18

480786

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

183386712

1

T1

429

T3

783

T18

479412

auto[1]

835584

1

T1

54

T3

36

T18

1380

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	192448	1			T18	1		T8	491		T38	1
all_values[0]	auto[0]	auto[1]	1900	1			T18	2		T8	6		T38	2
all_values[0]	auto[1]	auto[0]	60936456	1			T1	143		T3	261		T18	159803
all_values[0]	auto[1]	auto[1]	276628	1			T1	18		T3	12		T18	458
all_values[1]	auto[0]	auto[0]	154185	1			T3	5		T8	491		T9	1
all_values[1]	auto[0]	auto[1]	1467	1			T3	1		T8	6		T39	2
all_values[1]	auto[1]	auto[0]	60974719	1			T1	143		T3	256		T18	159804
all_values[1]	auto[1]	auto[1]	277061	1			T1	18		T3	11		T18	460
all_values[2]	auto[0]	auto[0]	160365	1			T1	65		T3	5		T18	1
all_values[2]	auto[0]	auto[1]	1414	1			T1	10		T3	1		T18	2
all_values[2]	auto[1]	auto[0]	60968539	1			T1	78		T3	256		T18	159803
all_values[2]	auto[1]	auto[1]	277114	1			T1	8		T3	11		T18	458