Unified Coverage Report :: Group :: kmac_env_pkg::config_masked_cg

Group : kmac_env_pkg::config_masked_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.88	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

---

Summary for Group kmac_env_pkg::config_masked_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	28	1	27	96.43
Crosses	4	0	4	100.00

Variables for Group kmac_env_pkg::config_masked_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
entropy_fast_process	2	0	2	100.00	100	1	1	2
entropy_mode	3	1	2	66.67	100	1	1	0
key_len	5	0	5	100.00	100	1	1	0
kmac_en	2	0	2	100.00	100	1	1	2
mode	3	0	3	100.00	100	1	1	0
msg_endian	2	0	2	100.00	100	1	1	2
sideload	2	0	2	100.00	100	1	1	2
state_endian	2	0	2	100.00	100	1	1	2
strength	5	0	5	100.00	100	1	1	0
xof_en	2	0	2	100.00	100	1	1	2

Crosses for Group kmac_env_pkg::config_masked_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
kmac_cross	1	0	1	100.00	100	1	1	0
cshake_cross	1	0	1	100.00	100	1	1	0
shake_cross	1	0	1	100.00	100	1	1	0
sha3_cross	1	0	1	100.00	100	1	1	0

Summary for Variable entropy_fast_process

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for entropy_fast_process

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

95392

1

T1

6

T3

8

T18

160

auto[1]

94959

1

T1

5

T3

1

T18

150

---

Summary for Variable entropy_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	1	2	66.67

Automatically Generated Bins for entropy_mode

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[EntropyModeNone]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[EntropyModeEdn]

98206

1

T18

310

T9

115

T39

310

auto[EntropyModeSw]

92145

1

T1

11

T3

9

T37

9

---

Summary for Variable key_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for key_len

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[Key128]	35254	1			T1	2		T18	71		T7	23
auto[Key192]	35204	1			T1	2		T18	64		T7	22
auto[Key256]	49563	1			T1	1		T3	9		T18	67
auto[Key384]	35277	1			T1	1		T18	50		T7	29
auto[Key512]	35053	1			T1	5		T18	58		T7	31

---

Summary for Variable kmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

159811

1

T1

3

T18

310

T7

88

auto[1]

30540

1

T1

8

T3

9

T37

9

---

Summary for Variable mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	0	3	100.00

Automatically Generated Bins for mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[Sha3]	60667	1			T18	310		T7	2		T8	5
auto[Shake]	95983	1			T1	3		T7	57		T8	30
auto[CShake]	33701	1			T1	8		T3	9		T37	9

---

Summary for Variable msg_endian

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for msg_endian

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

95554

1

T1

5

T3

3

T18

166

auto[1]

94797

1

T1

6

T3

6

T18

144

---

Summary for Variable sideload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sideload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

180389

1

T1

11

T3

9

T18

310

auto[1]

9962

1

T7

25

T8

24

T9

48

---

Summary for Variable state_endian

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for state_endian

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

95048

1

T1

5

T3

4

T18

158

auto[1]

95303

1

T1

6

T3

5

T18

152

---

Summary for Variable strength

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for strength

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[L128]	60609	1			T1	8		T3	6		T37	6
auto[L224]	15516	1			T7	1		T8	2		T40	4
auto[L256]	86581	1			T1	3		T3	3		T37	3
auto[L384]	15806	1			T18	310		T8	1		T9	1
auto[L512]	11839	1			T8	1		T38	246		T40	2

---

Summary for Variable xof_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for xof_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

172743

1

T1

7

T3

9

T18

310

auto[1]

17608

1

T1

4

T7

39

T8

72

---

Summary for Cross kmac_cross

Samples crossed: kmac_en xof_en strength key_len msg_endian state_endian entropy_mode entropy_fast_process

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
User Defined Cross Bins	1	0	1	100.00

User Defined Cross Bins for kmac_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid_mode	0	Excluded
invalid_strength	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valid

30540

1

T1

8

T3

9

T37

9

---

Summary for Cross cshake_cross

Samples crossed: mode strength msg_endian state_endian entropy_mode entropy_fast_process

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
User Defined Cross Bins	1	0	1	100.00

User Defined Cross Bins for cshake_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid_mode	0	Excluded
invalid_strength	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valid

33701

1

T1

8

T3

9

T37

9

---

Summary for Cross shake_cross

Samples crossed: mode strength msg_endian state_endian entropy_mode entropy_fast_process

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
User Defined Cross Bins	1	0	1	100.00

User Defined Cross Bins for shake_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid_mode	0	Excluded
invalid_strength	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valid

95983

1

T1

3

T7

57

T8

30

---

Summary for Cross sha3_cross

Samples crossed: mode strength msg_endian state_endian entropy_mode entropy_fast_process

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
User Defined Cross Bins	1	0	1	100.00

User Defined Cross Bins for sha3_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid_mode	0	Excluded
invalid_strength	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valid

60667

1

T18

310

T7

2

T8

5