Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
186678 |
1 |
|
|
T1 |
22 |
|
T3 |
18 |
|
T18 |
2 |
auto[1] |
197300 |
1 |
|
|
T18 |
618 |
|
T9 |
230 |
|
T39 |
618 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
95893 |
1 |
|
|
T1 |
7 |
|
T3 |
2 |
|
T18 |
148 |
lower_val |
95213 |
1 |
|
|
T1 |
6 |
|
T3 |
8 |
|
T18 |
152 |
zero_val |
1398 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T18 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
141576 |
1 |
|
|
T1 |
8 |
|
T3 |
10 |
|
T18 |
156 |
lower_val |
142934 |
1 |
|
|
T1 |
14 |
|
T3 |
8 |
|
T18 |
152 |
zero_val |
99468 |
1 |
|
|
T18 |
312 |
|
T9 |
110 |
|
T39 |
274 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
23215 |
1 |
|
|
T1 |
3 |
|
T3 |
1 |
|
T7 |
39 |
higher_val |
higher_val |
auto[1] |
12297 |
1 |
|
|
T18 |
32 |
|
T9 |
18 |
|
T39 |
44 |
higher_val |
lower_val |
auto[0] |
23387 |
1 |
|
|
T1 |
4 |
|
T3 |
1 |
|
T7 |
32 |
higher_val |
lower_val |
auto[1] |
12208 |
1 |
|
|
T18 |
36 |
|
T9 |
19 |
|
T39 |
60 |
higher_val |
zero_val |
auto[0] |
85 |
1 |
|
|
T39 |
1 |
|
T22 |
1 |
|
T41 |
1 |
higher_val |
zero_val |
auto[1] |
24701 |
1 |
|
|
T18 |
80 |
|
T9 |
30 |
|
T39 |
56 |
lower_val |
higher_val |
auto[0] |
22971 |
1 |
|
|
T1 |
3 |
|
T3 |
4 |
|
T37 |
1 |
lower_val |
higher_val |
auto[1] |
12241 |
1 |
|
|
T18 |
47 |
|
T9 |
12 |
|
T39 |
30 |
lower_val |
lower_val |
auto[0] |
23247 |
1 |
|
|
T1 |
3 |
|
T3 |
4 |
|
T37 |
5 |
lower_val |
lower_val |
auto[1] |
12133 |
1 |
|
|
T18 |
33 |
|
T9 |
15 |
|
T39 |
53 |
lower_val |
zero_val |
auto[0] |
66 |
1 |
|
|
T17 |
1 |
|
T192 |
1 |
|
T59 |
2 |
lower_val |
zero_val |
auto[1] |
24555 |
1 |
|
|
T18 |
72 |
|
T9 |
24 |
|
T39 |
69 |
zero_val |
higher_val |
auto[0] |
441 |
1 |
|
|
T8 |
1 |
|
T38 |
1 |
|
T9 |
1 |
zero_val |
higher_val |
auto[1] |
82 |
1 |
|
|
T67 |
1 |
|
T210 |
1 |
|
T130 |
1 |
zero_val |
lower_val |
auto[0] |
445 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T18 |
1 |
zero_val |
lower_val |
auto[1] |
96 |
1 |
|
|
T9 |
4 |
|
T17 |
1 |
|
T130 |
1 |
zero_val |
zero_val |
auto[0] |
225 |
1 |
|
|
T39 |
1 |
|
T22 |
1 |
|
T65 |
1 |
zero_val |
zero_val |
auto[1] |
109 |
1 |
|
|
T67 |
1 |
|
T210 |
1 |
|
T58 |
1 |