Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	61407432	1			T1	161		T3	273		T18	160264
all_pins[1]	61407432	1			T1	161		T3	273		T18	160264
all_pins[2]	61407432	1			T1	161		T3	273		T18	160264

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	183704251	1			T1	465		T3	807		T18	480334
values[0x1]	518045	1			T1	18		T3	12		T18	458
transitions[0x0=>0x1]	516462	1			T1	18		T3	12		T18	458
transitions[0x1=>0x0]	516493	1			T1	18		T3	12		T18	458

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	61130804	1			T1	143		T3	261		T18	159806
all_pins[0]	values[0x1]	276628	1			T1	18		T3	12		T18	458
all_pins[0]	transitions[0x0=>0x1]	276621	1			T1	18		T3	12		T18	458
all_pins[0]	transitions[0x1=>0x0]	5331	1			T8	82		T22	46		T21	4
all_pins[1]	values[0x0]	61402094	1			T1	161		T3	273		T18	160264
all_pins[1]	values[0x1]	5338	1			T8	82		T22	46		T21	4
all_pins[1]	transitions[0x0=>0x1]	5164	1			T8	81		T22	46		T21	4
all_pins[1]	transitions[0x1=>0x0]	235905	1			T8	1419		T9	710		T22	656
all_pins[2]	values[0x0]	61171353	1			T1	161		T3	273		T18	160264
all_pins[2]	values[0x1]	236079	1			T8	1420		T9	710		T22	656
all_pins[2]	transitions[0x0=>0x1]	234677	1			T8	1420		T9	707		T22	656
all_pins[2]	transitions[0x1=>0x0]	275257	1			T1	18		T3	12		T18	458