Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	625	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5148	1			T1	2		T7	21		T8	25
len_601_800	11528	1			T1	5		T7	40		T8	45
len_401_600	7830	1			T1	3		T7	28		T8	34
len_201_400	8797	1			T1	1		T7	16		T8	16
len_65_200	30233	1			T7	8		T8	4		T9	8
len_min_for_xof_require_squeeze	395	1			T41	9		T158	9		T147	9
len_keccak_block_sizes[72]	309	1			T41	9		T67	1		T158	9
len_keccak_block_sizes[104]	300	1			T40	2		T41	9		T158	9
len_keccak_block_sizes[136]	295	1			T9	1		T41	9		T158	9
len_keccak_block_sizes[144]	139	1			T40	1		T129	1		T106	1
len_keccak_block_sizes[168]	131	1			T76	1		T184	1		T211	1
len_datapath_width	12796	1			T3	3		T37	3		T8	1
len_2_63	113339	1			T3	6		T18	310		T37	6
len_1	55	1			T40	1		T127	1		T212	1