Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	57835806	1			T2	3237		T3	18927		T15	293186
all_values[1]	57835806	1			T2	3237		T3	18927		T15	293186
all_values[2]	57835806	1			T2	3237		T3	18927		T15	293186

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

413574

1

T2

210

T20

928

T31

74

auto[1]

173093844

1

T2

9501

T3

56781

T15

879558

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

172716495

1

T2

9528

T3

56241

T15

878697

auto[1]

790923

1

T2

183

T3

540

T15

861

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	134857	1			T32	1		T37	55		T38	7
all_values[0]	auto[0]	auto[1]	2037	1			T32	2		T37	8		T38	2
all_values[0]	auto[1]	auto[0]	57437308	1			T2	3176		T3	18747		T15	292899
all_values[0]	auto[1]	auto[1]	261604	1			T2	61		T3	180		T15	287
all_values[1]	auto[0]	auto[0]	140594	1			T2	204		T20	233		T31	63
all_values[1]	auto[0]	auto[1]	1359	1			T2	1		T20	1		T31	5
all_values[1]	auto[1]	auto[0]	57431571	1			T2	2972		T3	18747		T15	292899
all_values[1]	auto[1]	auto[1]	262282	1			T2	60		T3	180		T15	287
all_values[2]	auto[0]	auto[0]	133309	1			T2	5		T20	691		T31	5
all_values[2]	auto[0]	auto[1]	1418	1			T20	3		T31	1		T33	1
all_values[2]	auto[1]	auto[0]	57438856	1			T2	3171		T3	18747		T15	292899
all_values[2]	auto[1]	auto[1]	262223	1			T2	61		T3	180		T15	287