Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
162336 |
1 |
|
|
T2 |
36 |
|
T3 |
2 |
|
T15 |
2 |
auto[1] |
202772 |
1 |
|
|
T2 |
66 |
|
T3 |
260 |
|
T15 |
374 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
90899 |
1 |
|
|
T2 |
11 |
|
T3 |
64 |
|
T15 |
86 |
lower_val |
90005 |
1 |
|
|
T2 |
28 |
|
T3 |
55 |
|
T15 |
80 |
zero_val |
1427 |
1 |
|
|
T2 |
2 |
|
T3 |
1 |
|
T15 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
131186 |
1 |
|
|
T2 |
32 |
|
T3 |
56 |
|
T15 |
88 |
lower_val |
132298 |
1 |
|
|
T2 |
34 |
|
T3 |
64 |
|
T15 |
100 |
zero_val |
101624 |
1 |
|
|
T2 |
36 |
|
T3 |
142 |
|
T15 |
188 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
20103 |
1 |
|
|
T2 |
3 |
|
T20 |
28 |
|
T33 |
597 |
higher_val |
higher_val |
auto[1] |
12794 |
1 |
|
|
T3 |
12 |
|
T15 |
15 |
|
T31 |
2 |
higher_val |
lower_val |
auto[0] |
20008 |
1 |
|
|
T2 |
4 |
|
T15 |
1 |
|
T20 |
32 |
higher_val |
lower_val |
auto[1] |
12675 |
1 |
|
|
T3 |
17 |
|
T15 |
22 |
|
T32 |
34 |
higher_val |
zero_val |
auto[0] |
69 |
1 |
|
|
T185 |
1 |
|
T145 |
1 |
|
T63 |
1 |
higher_val |
zero_val |
auto[1] |
25250 |
1 |
|
|
T2 |
4 |
|
T3 |
35 |
|
T15 |
48 |
lower_val |
higher_val |
auto[0] |
20050 |
1 |
|
|
T2 |
4 |
|
T20 |
31 |
|
T33 |
546 |
lower_val |
higher_val |
auto[1] |
12511 |
1 |
|
|
T2 |
1 |
|
T3 |
13 |
|
T15 |
20 |
lower_val |
lower_val |
auto[0] |
19814 |
1 |
|
|
T2 |
1 |
|
T20 |
29 |
|
T33 |
560 |
lower_val |
lower_val |
auto[1] |
12568 |
1 |
|
|
T2 |
7 |
|
T3 |
13 |
|
T15 |
21 |
lower_val |
zero_val |
auto[0] |
66 |
1 |
|
|
T2 |
1 |
|
T30 |
1 |
|
T11 |
1 |
lower_val |
zero_val |
auto[1] |
24996 |
1 |
|
|
T2 |
14 |
|
T3 |
29 |
|
T15 |
39 |
zero_val |
higher_val |
auto[0] |
409 |
1 |
|
|
T2 |
1 |
|
T33 |
3 |
|
T62 |
1 |
zero_val |
higher_val |
auto[1] |
104 |
1 |
|
|
T186 |
1 |
|
T13 |
1 |
|
T66 |
2 |
zero_val |
lower_val |
auto[0] |
450 |
1 |
|
|
T2 |
1 |
|
T15 |
1 |
|
T20 |
1 |
zero_val |
lower_val |
auto[1] |
105 |
1 |
|
|
T38 |
1 |
|
T16 |
1 |
|
T13 |
2 |
zero_val |
zero_val |
auto[0] |
219 |
1 |
|
|
T3 |
1 |
|
T31 |
1 |
|
T32 |
1 |
zero_val |
zero_val |
auto[1] |
140 |
1 |
|
|
T38 |
1 |
|
T186 |
1 |
|
T16 |
1 |