Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	57835806	1			T2	3237		T3	18927		T15	293186
all_pins[1]	57835806	1			T2	3237		T3	18927		T15	293186
all_pins[2]	57835806	1			T2	3237		T3	18927		T15	293186

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	172977254	1			T2	9557		T3	56107		T15	879184
values[0x1]	530164	1			T2	154		T3	674		T15	374
transitions[0x0=>0x1]	528384	1			T2	151		T3	674		T15	374
transitions[0x1=>0x0]	528410	1			T2	151		T3	674		T15	374

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	57574202	1			T2	3176		T3	18747		T15	292899
all_pins[0]	values[0x1]	261604	1			T2	61		T3	180		T15	287
all_pins[0]	transitions[0x0=>0x1]	261594	1			T2	61		T3	180		T15	287
all_pins[0]	transitions[0x1=>0x0]	5916	1			T2	3		T15	87		T20	49
all_pins[1]	values[0x0]	57829880	1			T2	3234		T3	18927		T15	293099
all_pins[1]	values[0x1]	5926	1			T2	3		T15	87		T20	49
all_pins[1]	transitions[0x0=>0x1]	5720	1			T2	1		T15	87		T20	49
all_pins[1]	transitions[0x1=>0x0]	262428	1			T2	88		T3	494		T6	1000
all_pins[2]	values[0x0]	57573172	1			T2	3147		T3	18433		T15	293186
all_pins[2]	values[0x1]	262634	1			T2	90		T3	494		T6	1000
all_pins[2]	transitions[0x0=>0x1]	261070	1			T2	89		T3	494		T6	999
all_pins[2]	transitions[0x1=>0x0]	260066	1			T2	60		T3	180		T15	287