Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7850973 |
1 |
|
|
T2 |
3861 |
|
T3 |
19698 |
|
T15 |
31703 |
auto[1] |
7850970 |
1 |
|
|
T2 |
3861 |
|
T3 |
19698 |
|
T15 |
31703 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
15586145 |
1 |
|
|
T2 |
7662 |
|
T3 |
39206 |
|
T15 |
63134 |
triple_byte_access |
38418 |
1 |
|
|
T2 |
22 |
|
T3 |
76 |
|
T15 |
92 |
halfword_access |
38852 |
1 |
|
|
T2 |
14 |
|
T3 |
64 |
|
T15 |
104 |
byte_access |
38528 |
1 |
|
|
T2 |
24 |
|
T3 |
50 |
|
T15 |
76 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
7793074 |
1 |
|
|
T2 |
3831 |
|
T3 |
19603 |
|
T15 |
31567 |
auto[0] |
triple_byte_access |
19209 |
1 |
|
|
T2 |
11 |
|
T3 |
38 |
|
T15 |
46 |
auto[0] |
halfword_access |
19426 |
1 |
|
|
T2 |
7 |
|
T3 |
32 |
|
T15 |
52 |
auto[0] |
byte_access |
19264 |
1 |
|
|
T2 |
12 |
|
T3 |
25 |
|
T15 |
38 |
auto[1] |
word_access |
7793071 |
1 |
|
|
T2 |
3831 |
|
T3 |
19603 |
|
T15 |
31567 |
auto[1] |
triple_byte_access |
19209 |
1 |
|
|
T2 |
11 |
|
T3 |
38 |
|
T15 |
46 |
auto[1] |
halfword_access |
19426 |
1 |
|
|
T2 |
7 |
|
T3 |
32 |
|
T15 |
52 |
auto[1] |
byte_access |
19264 |
1 |
|
|
T2 |
12 |
|
T3 |
25 |
|
T15 |
38 |