Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	64709762	1			T1	161134		T2	41609		T3	2
all_values[1]	64709762	1			T1	161134		T2	41609		T3	2
all_values[2]	64709762	1			T1	161134		T2	41609		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

437224

1

T1

14

T2

6096

T3

2

auto[1]

193692062

1

T1

483388

T2

118731

T3

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

193239156

1

T1

482022

T2

124695

T3

6

auto[1]

890130

1

T1

1380

T2

132

T6

75

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	141090	1			T1	1		T2	3485		T4	7626
all_values[0]	auto[0]	auto[1]	1898	1			T1	2		T2	6		T4	32
all_values[0]	auto[1]	auto[0]	64271962	1			T1	160673		T2	38080		T3	2
all_values[0]	auto[1]	auto[1]	294812	1			T1	458		T2	38		T6	25
all_values[1]	auto[0]	auto[0]	143407	1			T1	7		T2	95		T6	2323
all_values[1]	auto[0]	auto[1]	1454	1			T1	4		T2	2		T6	1
all_values[1]	auto[1]	auto[0]	64269645	1			T1	160667		T2	41470		T3	2
all_values[1]	auto[1]	auto[1]	295256	1			T1	456		T2	42		T6	24
all_values[2]	auto[0]	auto[0]	147875	1			T2	2504		T3	2		T6	2323
all_values[2]	auto[0]	auto[1]	1500	1			T2	4		T6	1		T12	1
all_values[2]	auto[1]	auto[0]	64265177	1			T1	160674		T2	39061		T6	25477
all_values[2]	auto[1]	auto[1]	295210	1			T1	460		T2	40		T6	24