Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
225678 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
2 |
auto[1] |
183410 |
1 |
|
|
T1 |
618 |
|
T2 |
52 |
|
T38 |
16 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
102769 |
1 |
|
|
T1 |
146 |
|
T2 |
12 |
|
T3 |
1 |
lower_val |
100479 |
1 |
|
|
T1 |
170 |
|
T2 |
14 |
|
T6 |
7 |
zero_val |
1466 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
158318 |
1 |
|
|
T1 |
140 |
|
T2 |
12 |
|
T6 |
18 |
lower_val |
158976 |
1 |
|
|
T1 |
146 |
|
T2 |
14 |
|
T3 |
2 |
zero_val |
91794 |
1 |
|
|
T1 |
334 |
|
T2 |
28 |
|
T38 |
10 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
27976 |
1 |
|
|
T6 |
2 |
|
T12 |
38 |
|
T4 |
51 |
higher_val |
higher_val |
auto[1] |
11532 |
1 |
|
|
T1 |
30 |
|
T2 |
3 |
|
T4 |
15 |
higher_val |
lower_val |
auto[0] |
28482 |
1 |
|
|
T3 |
1 |
|
T6 |
4 |
|
T12 |
34 |
higher_val |
lower_val |
auto[1] |
11682 |
1 |
|
|
T1 |
33 |
|
T2 |
5 |
|
T4 |
37 |
higher_val |
zero_val |
auto[0] |
92 |
1 |
|
|
T2 |
1 |
|
T4 |
3 |
|
T41 |
1 |
higher_val |
zero_val |
auto[1] |
23005 |
1 |
|
|
T1 |
83 |
|
T2 |
3 |
|
T4 |
58 |
lower_val |
higher_val |
auto[0] |
27571 |
1 |
|
|
T6 |
3 |
|
T12 |
54 |
|
T4 |
47 |
lower_val |
higher_val |
auto[1] |
11372 |
1 |
|
|
T1 |
45 |
|
T2 |
3 |
|
T38 |
1 |
lower_val |
lower_val |
auto[0] |
27594 |
1 |
|
|
T6 |
4 |
|
T12 |
51 |
|
T4 |
43 |
lower_val |
lower_val |
auto[1] |
11328 |
1 |
|
|
T1 |
39 |
|
T2 |
6 |
|
T38 |
1 |
lower_val |
zero_val |
auto[0] |
71 |
1 |
|
|
T197 |
1 |
|
T11 |
1 |
|
T24 |
3 |
lower_val |
zero_val |
auto[1] |
22543 |
1 |
|
|
T1 |
86 |
|
T2 |
5 |
|
T38 |
4 |
zero_val |
higher_val |
auto[0] |
451 |
1 |
|
|
T4 |
3 |
|
T42 |
2 |
|
T5 |
1 |
zero_val |
higher_val |
auto[1] |
105 |
1 |
|
|
T5 |
1 |
|
T11 |
4 |
|
T24 |
1 |
zero_val |
lower_val |
auto[0] |
462 |
1 |
|
|
T3 |
1 |
|
T6 |
1 |
|
T12 |
1 |
zero_val |
lower_val |
auto[1] |
95 |
1 |
|
|
T4 |
4 |
|
T11 |
1 |
|
T24 |
4 |
zero_val |
zero_val |
auto[0] |
225 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T41 |
1 |
zero_val |
zero_val |
auto[1] |
128 |
1 |
|
|
T4 |
2 |
|
T41 |
2 |
|
T13 |
2 |