Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	64709762	1			T1	161134		T2	41609		T3	2
all_pins[1]	64709762	1			T1	161134		T2	41609		T3	2
all_pins[2]	64709762	1			T1	161134		T2	41609		T3	2

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	193587856	1			T1	482944		T2	124779		T3	6
values[0x1]	541430	1			T1	458		T2	48		T6	25
transitions[0x0=>0x1]	539759	1			T1	458		T2	48		T6	25
transitions[0x1=>0x0]	539780	1			T1	458		T2	48		T6	25

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	64414950	1			T1	160676		T2	41571		T3	2
all_pins[0]	values[0x1]	294812	1			T1	458		T2	38		T6	25
all_pins[0]	transitions[0x0=>0x1]	294801	1			T1	458		T2	38		T6	25
all_pins[0]	transitions[0x1=>0x0]	4974	1			T2	10		T27	41		T15	12
all_pins[1]	values[0x0]	64704777	1			T1	161134		T2	41599		T3	2
all_pins[1]	values[0x1]	4985	1			T2	10		T27	41		T15	12
all_pins[1]	transitions[0x0=>0x1]	4756	1			T2	10		T27	41		T15	12
all_pins[1]	transitions[0x1=>0x0]	241404	1			T4	5891		T11	1940		T24	5721
all_pins[2]	values[0x0]	64468129	1			T1	161134		T2	41609		T3	2
all_pins[2]	values[0x1]	241633	1			T4	5891		T11	1940		T24	5721
all_pins[2]	transitions[0x0=>0x1]	240202	1			T4	5845		T11	1926		T24	5681
all_pins[2]	transitions[0x1=>0x0]	293402	1			T1	458		T2	38		T6	25