Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	597	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5001	1			T2	2		T6	1		T12	33
len_601_800	11454	1			T2	12		T6	8		T12	74
len_401_600	7502	1			T2	3		T6	4		T12	39
len_201_400	7817	1			T2	3		T12	20		T4	25
len_65_200	33124	1			T2	5		T6	1		T12	12
len_min_for_xof_require_squeeze	445	1			T5	1		T43	9		T156	1
len_keccak_block_sizes[72]	359	1			T4	1		T5	1		T43	9
len_keccak_block_sizes[104]	350	1			T4	1		T5	1		T43	9
len_keccak_block_sizes[136]	352	1			T43	9		T11	1		T198	5
len_keccak_block_sizes[144]	111	1			T12	2		T64	2		T199	1
len_keccak_block_sizes[168]	120	1			T198	5		T129	1		T61	1
len_datapath_width	13641	1			T38	3		T4	10		T39	3
len_2_63	123661	1			T1	310		T2	1		T6	1
len_1	46	1			T4	1		T15	1		T199	1