Summary for Variable share
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for share
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
7871617 | 
1 | 
 | 
 | 
T1 | 
3720 | 
 | 
T2 | 
4022 | 
 | 
T6 | 
2876 | 
| auto[1] | 
7871494 | 
1 | 
 | 
 | 
T1 | 
3720 | 
 | 
T2 | 
4022 | 
 | 
T6 | 
2876 | 
Summary for Variable state_read_mask
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
4 | 
0 | 
4 | 
100.00 | 
User Defined Bins for state_read_mask
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| word_access | 
15615155 | 
1 | 
 | 
 | 
T1 | 
7440 | 
 | 
T2 | 
8004 | 
 | 
T6 | 
5728 | 
| triple_byte_access | 
42450 | 
1 | 
 | 
 | 
T2 | 
16 | 
 | 
T6 | 
8 | 
 | 
T12 | 
100 | 
| halfword_access | 
42736 | 
1 | 
 | 
 | 
T2 | 
8 | 
 | 
T6 | 
6 | 
 | 
T12 | 
92 | 
| byte_access | 
42770 | 
1 | 
 | 
 | 
T2 | 
16 | 
 | 
T6 | 
10 | 
 | 
T12 | 
104 | 
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
8 | 
0 | 
8 | 
100.00 | 
 | 
Automatically Generated Cross Bins for state_mask_share_cross
Bins
| share | state_read_mask | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
word_access | 
7807639 | 
1 | 
 | 
 | 
T1 | 
3720 | 
 | 
T2 | 
4002 | 
 | 
T6 | 
2864 | 
| auto[0] | 
triple_byte_access | 
21225 | 
1 | 
 | 
 | 
T2 | 
8 | 
 | 
T6 | 
4 | 
 | 
T12 | 
50 | 
| auto[0] | 
halfword_access | 
21368 | 
1 | 
 | 
 | 
T2 | 
4 | 
 | 
T6 | 
3 | 
 | 
T12 | 
46 | 
| auto[0] | 
byte_access | 
21385 | 
1 | 
 | 
 | 
T2 | 
8 | 
 | 
T6 | 
5 | 
 | 
T12 | 
52 | 
| auto[1] | 
word_access | 
7807516 | 
1 | 
 | 
 | 
T1 | 
3720 | 
 | 
T2 | 
4002 | 
 | 
T6 | 
2864 | 
| auto[1] | 
triple_byte_access | 
21225 | 
1 | 
 | 
 | 
T2 | 
8 | 
 | 
T6 | 
4 | 
 | 
T12 | 
50 | 
| auto[1] | 
halfword_access | 
21368 | 
1 | 
 | 
 | 
T2 | 
4 | 
 | 
T6 | 
3 | 
 | 
T12 | 
46 | 
| auto[1] | 
byte_access | 
21385 | 
1 | 
 | 
 | 
T2 | 
8 | 
 | 
T6 | 
5 | 
 | 
T12 | 
52 |