Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	62147949	1			T1	213321		T2	210892		T20	6998
all_values[1]	62147949	1			T1	213321		T2	210892		T20	6998
all_values[2]	62147949	1			T1	213321		T2	210892		T20	6998

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

377654

1

T1

13

T2

6

T20

75

auto[1]

186066193

1

T1

639950

T2

632670

T20

20919

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

185570328

1

T1

638226

T2

630981

T20

20805

auto[1]

873519

1

T1

1737

T2

1695

T20

189

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	114249	1			T1	3		T7	1		T34	62
all_values[0]	auto[0]	auto[1]	1806	1			T1	4		T34	8		T36	2
all_values[0]	auto[1]	auto[0]	61742527	1			T1	212739		T2	210327		T20	6935
all_values[0]	auto[1]	auto[1]	289367	1			T1	575		T2	565		T20	63
all_values[1]	auto[0]	auto[0]	125123	1			T1	1		T2	2		T20	74
all_values[1]	auto[0]	auto[1]	1336	1			T1	2		T2	1		T20	1
all_values[1]	auto[1]	auto[0]	61731653	1			T1	212741		T2	210325		T20	6861
all_values[1]	auto[1]	auto[1]	289837	1			T1	577		T2	564		T20	62
all_values[2]	auto[0]	auto[0]	133723	1			T1	1		T2	2		T34	22
all_values[2]	auto[0]	auto[1]	1417	1			T1	2		T2	1		T34	2
all_values[2]	auto[1]	auto[0]	61723053	1			T1	212741		T2	210325		T20	6935
all_values[2]	auto[1]	auto[1]	289756	1			T1	577		T2	564		T20	63