Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	62147949	1			T1	213321		T2	210892		T20	6998
all_pins[1]	62147949	1			T1	213321		T2	210892		T20	6998
all_pins[2]	62147949	1			T1	213321		T2	210892		T20	6998

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	185910144	1			T1	639388		T2	632111		T20	20931
values[0x1]	533703	1			T1	575		T2	565		T20	63
transitions[0x0=>0x1]	532062	1			T1	575		T2	565		T20	63
transitions[0x1=>0x0]	532077	1			T1	575		T2	565		T20	63

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	61858582	1			T1	212746		T2	210327		T20	6935
all_pins[0]	values[0x1]	289367	1			T1	575		T2	565		T20	63
all_pins[0]	transitions[0x0=>0x1]	289348	1			T1	575		T2	565		T20	63
all_pins[0]	transitions[0x1=>0x0]	4812	1			T7	1		T36	1		T37	42
all_pins[1]	values[0x0]	62143118	1			T1	213321		T2	210892		T20	6998
all_pins[1]	values[0x1]	4831	1			T7	1		T36	1		T37	42
all_pins[1]	transitions[0x0=>0x1]	4643	1			T7	1		T36	1		T37	42
all_pins[1]	transitions[0x1=>0x0]	239317	1			T8	3681		T15	4543		T21	205
all_pins[2]	values[0x0]	61908444	1			T1	213321		T2	210892		T20	6998
all_pins[2]	values[0x1]	239505	1			T8	3683		T15	4553		T21	205
all_pins[2]	transitions[0x0=>0x1]	238071	1			T8	3664		T15	4521		T21	205
all_pins[2]	transitions[0x1=>0x0]	287948	1			T1	575		T2	565		T20	63