Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7885086 |
1 |
|
|
T1 |
2992 |
|
T2 |
2992 |
|
T20 |
7800 |
auto[1] |
7885086 |
1 |
|
|
T1 |
2992 |
|
T2 |
2992 |
|
T20 |
7800 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
15641254 |
1 |
|
|
T1 |
5984 |
|
T2 |
5984 |
|
T20 |
15534 |
triple_byte_access |
43172 |
1 |
|
|
T20 |
14 |
|
T7 |
2 |
|
T35 |
558 |
halfword_access |
42890 |
1 |
|
|
T20 |
28 |
|
T7 |
10 |
|
T35 |
558 |
byte_access |
42856 |
1 |
|
|
T20 |
24 |
|
T35 |
558 |
|
T34 |
78 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
7820627 |
1 |
|
|
T1 |
2992 |
|
T2 |
2992 |
|
T20 |
7767 |
auto[0] |
triple_byte_access |
21586 |
1 |
|
|
T20 |
7 |
|
T7 |
1 |
|
T35 |
279 |
auto[0] |
halfword_access |
21445 |
1 |
|
|
T20 |
14 |
|
T7 |
5 |
|
T35 |
279 |
auto[0] |
byte_access |
21428 |
1 |
|
|
T20 |
12 |
|
T35 |
279 |
|
T34 |
39 |
auto[1] |
word_access |
7820627 |
1 |
|
|
T1 |
2992 |
|
T2 |
2992 |
|
T20 |
7767 |
auto[1] |
triple_byte_access |
21586 |
1 |
|
|
T20 |
7 |
|
T7 |
1 |
|
T35 |
279 |
auto[1] |
halfword_access |
21445 |
1 |
|
|
T20 |
14 |
|
T7 |
5 |
|
T35 |
279 |
auto[1] |
byte_access |
21428 |
1 |
|
|
T20 |
12 |
|
T35 |
279 |
|
T34 |
39 |