Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	63124963	1			T1	52395		T7	93623		T16	4733
all_values[1]	63124963	1			T1	52395		T7	93623		T16	4733
all_values[2]	63124963	1			T1	52395		T7	93623		T16	4733

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

467100

1

T1

479

T7

2562

T8

10668

auto[1]

188907789

1

T1

156706

T7

278307

T16

14199

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

188470668

1

T1

156372

T7

279597

T16

14067

auto[1]

904221

1

T1

813

T7

1272

T16

132

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	160574	1			T1	229		T7	444		T8	5208
all_values[0]	auto[0]	auto[1]	1866	1			T1	8		T7	12		T8	6
all_values[0]	auto[1]	auto[0]	62662982	1			T1	51895		T7	92755		T16	4689
all_values[0]	auto[1]	auto[1]	299541	1			T1	263		T7	412		T16	44
all_values[1]	auto[0]	auto[0]	137929	1			T1	239		T7	1164		T8	1729
all_values[1]	auto[0]	auto[1]	1252	1			T1	1		T7	18		T8	2
all_values[1]	auto[1]	auto[0]	62685627	1			T1	51885		T7	92035		T16	4689
all_values[1]	auto[1]	auto[1]	300155	1			T1	270		T7	406		T16	44
all_values[2]	auto[0]	auto[0]	164039	1			T1	2		T7	906		T8	3719
all_values[2]	auto[0]	auto[1]	1440	1			T7	18		T8	4		T35	8
all_values[2]	auto[1]	auto[0]	62659517	1			T1	52122		T7	92293		T16	4689
all_values[2]	auto[1]	auto[1]	299967	1			T1	271		T7	406		T16	44