Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
226422 |
1 |
|
|
T1 |
272 |
|
T7 |
494 |
|
T16 |
2 |
auto[1] |
188332 |
1 |
|
|
T1 |
150 |
|
T7 |
194 |
|
T16 |
56 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
103973 |
1 |
|
|
T1 |
118 |
|
T7 |
179 |
|
T16 |
13 |
lower_val |
102739 |
1 |
|
|
T1 |
85 |
|
T7 |
147 |
|
T16 |
18 |
zero_val |
1445 |
1 |
|
|
T1 |
6 |
|
T7 |
9 |
|
T16 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
159918 |
1 |
|
|
T1 |
166 |
|
T7 |
306 |
|
T16 |
14 |
lower_val |
160464 |
1 |
|
|
T1 |
166 |
|
T7 |
284 |
|
T16 |
26 |
zero_val |
94372 |
1 |
|
|
T1 |
90 |
|
T7 |
98 |
|
T16 |
18 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
28301 |
1 |
|
|
T1 |
33 |
|
T7 |
73 |
|
T8 |
28 |
higher_val |
higher_val |
auto[1] |
11890 |
1 |
|
|
T1 |
11 |
|
T7 |
14 |
|
T16 |
5 |
higher_val |
lower_val |
auto[0] |
28177 |
1 |
|
|
T1 |
33 |
|
T7 |
63 |
|
T8 |
26 |
higher_val |
lower_val |
auto[1] |
11862 |
1 |
|
|
T1 |
9 |
|
T7 |
16 |
|
T16 |
4 |
higher_val |
zero_val |
auto[0] |
63 |
1 |
|
|
T1 |
2 |
|
T55 |
1 |
|
T148 |
1 |
higher_val |
zero_val |
auto[1] |
23680 |
1 |
|
|
T1 |
30 |
|
T7 |
13 |
|
T16 |
4 |
lower_val |
higher_val |
auto[0] |
27736 |
1 |
|
|
T1 |
38 |
|
T7 |
59 |
|
T8 |
25 |
lower_val |
higher_val |
auto[1] |
11688 |
1 |
|
|
T1 |
6 |
|
T7 |
11 |
|
T16 |
4 |
lower_val |
lower_val |
auto[0] |
27982 |
1 |
|
|
T1 |
27 |
|
T7 |
44 |
|
T8 |
31 |
lower_val |
lower_val |
auto[1] |
11875 |
1 |
|
|
T1 |
3 |
|
T7 |
14 |
|
T16 |
9 |
lower_val |
zero_val |
auto[0] |
54 |
1 |
|
|
T65 |
1 |
|
T184 |
1 |
|
T185 |
1 |
lower_val |
zero_val |
auto[1] |
23404 |
1 |
|
|
T1 |
11 |
|
T7 |
19 |
|
T16 |
5 |
zero_val |
higher_val |
auto[0] |
432 |
1 |
|
|
T1 |
2 |
|
T7 |
4 |
|
T8 |
1 |
zero_val |
higher_val |
auto[1] |
108 |
1 |
|
|
T1 |
2 |
|
T186 |
1 |
|
T15 |
1 |
zero_val |
lower_val |
auto[0] |
481 |
1 |
|
|
T1 |
1 |
|
T7 |
2 |
|
T16 |
1 |
zero_val |
lower_val |
auto[1] |
90 |
1 |
|
|
T7 |
1 |
|
T187 |
1 |
|
T39 |
1 |
zero_val |
zero_val |
auto[0] |
213 |
1 |
|
|
T1 |
1 |
|
T7 |
1 |
|
T55 |
1 |
zero_val |
zero_val |
auto[1] |
121 |
1 |
|
|
T7 |
1 |
|
T187 |
1 |
|
T186 |
1 |