Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	5773	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	6313	1			T1	10		T7	8		T8	10
len_5001_7500	11012	1			T1	38		T7	22		T8	21
len_2501_5000	6861	1			T1	7		T7	3		T8	5
len_1025_2500	4032	1			T1	4		T8	4		T34	3
len_769_1024	5905	1			T1	13		T7	47		T16	8
len_513_768	6465	1			T1	17		T7	49		T16	9
len_257_512	12265	1			T1	17		T7	50		T16	9
len_0_256	142166	1			T1	76		T7	113		T16	3
len_keccak_block_sizes[72]	516	1			T54	2		T55	2		T188	2
len_keccak_block_sizes[104]	413	1			T1	1		T54	2		T55	2
len_keccak_block_sizes[136]	316	1			T55	2		T189	2		T186	2
len_keccak_block_sizes[144]	225	1			T7	1		T55	2		T189	2
len_keccak_block_sizes[168]	157	1			T190	1		T191	3		T192	3
len_1	546	1			T54	2		T55	2		T125	1
len_0	951	1			T1	1		T7	1		T8	1