Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

Group : kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

---

Summary for Group kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hash_mode	3	0	3	100.00	100	1	1	0
kmac_mode	2	0	2	100.00	100	1	1	2
msgfifo_depth	11	0	11	100.00	100	1	1	0
msgfifo_empty	2	0	2	100.00	100	1	1	2
msgfifo_full	2	0	2	100.00	100	1	1	2

Summary for Variable hash_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for hash_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
cshake	12984635	1			T1	106138		T7	64724		T16	4065
shake	27739322	1			T1	30985		T7	31706		T16	1492
sha3	31127198	1			T1	1371		T7	4571		T8	233

---

Summary for Variable kmac_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_mode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58865513

1

T1

32356

T7

36270

T16

1492

auto[1]

12985642

1

T1

106138

T7

64731

T16

4065

---

Summary for Variable msgfifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for msgfifo_depth

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
depth[0x00]	56031388	1			T1	62104		T7	99865		T16	5466
depth[0x01]	3170645	1			T1	6872		T7	1013		T16	77
depth[0x02]	3148458	1			T1	10300		T7	114		T16	13
depth[0x03]	2944170	1			T1	10123		T7	4		T16	1
depth[0x04]	2642220	1			T1	8710		T7	1		T8	2
depth[0x05]	1525975	1			T1	7517		T8	2		T11	2
depth[0x06]	485549	1			T1	6589		T8	2		T11	1
depth[0x07]	404138	1			T1	5559		T8	2		T34	5673
depth[0x08]	397490	1			T1	5604		T8	2		T34	5664
depth[0x09]	375743	1			T1	5270		T8	2		T34	5448
depth[0x0a]	725379	1			T1	9846		T7	4		T8	28

---

Summary for Variable msgfifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for msgfifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15819767

1

T1

76390

T7

1136

T16

91

auto[1]

56031388

1

T1

62104

T7

99865

T16

5466

---

Summary for Variable msgfifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for msgfifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

71125776

1

T1

128648

T7

100997

T16

5557

auto[1]

725379

1

T1

9846

T7

4

T8

28