Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	63124963	1			T1	52395		T7	93623		T16	4733
all_pins[1]	63124963	1			T1	52395		T7	93623		T16	4733
all_pins[2]	63124963	1			T1	52395		T7	93623		T16	4733

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	188802238	1			T1	154502		T7	271878		T16	14155
values[0x1]	572651	1			T1	2683		T7	8991		T16	44
transitions[0x0=>0x1]	570932	1			T1	2665		T7	8931		T16	44
transitions[0x1=>0x0]	570954	1			T1	2665		T7	8931		T16	44

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	62825422	1			T1	52132		T7	93211		T16	4689
all_pins[0]	values[0x1]	299541	1			T1	263		T7	412		T16	44
all_pins[0]	transitions[0x0=>0x1]	299526	1			T1	263		T7	412		T16	44
all_pins[0]	transitions[0x1=>0x0]	5087	1			T1	61		T34	8		T19	10
all_pins[1]	values[0x0]	63119861	1			T1	52334		T7	93623		T16	4733
all_pins[1]	values[0x1]	5102	1			T1	61		T34	8		T19	10
all_pins[1]	transitions[0x0=>0x1]	5008	1			T1	57		T34	8		T19	10
all_pins[1]	transitions[0x1=>0x0]	267914	1			T1	2355		T7	8579		T20	766
all_pins[2]	values[0x0]	62856955	1			T1	50036		T7	85044		T16	4733
all_pins[2]	values[0x1]	268008	1			T1	2359		T7	8579		T20	766
all_pins[2]	transitions[0x0=>0x1]	266398	1			T1	2345		T7	8519		T20	766
all_pins[2]	transitions[0x1=>0x0]	297953	1			T1	249		T7	352		T16	44