Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	557	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5128	1			T1	19		T7	39		T16	4
len_601_800	11643	1			T1	41		T7	82		T16	10
len_401_600	7633	1			T1	32		T7	58		T16	8
len_201_400	9632	1			T1	18		T7	28		T16	2
len_65_200	35390	1			T1	36		T7	28		T16	5
len_min_for_xof_require_squeeze	484	1			T1	1		T7	1		T148	1
len_keccak_block_sizes[72]	356	1			T36	3		T114	2		T115	1
len_keccak_block_sizes[104]	351	1			T1	1		T148	1		T193	1
len_keccak_block_sizes[136]	366	1			T16	1		T148	2		T193	1
len_keccak_block_sizes[144]	147	1			T36	1		T191	5		T192	5
len_keccak_block_sizes[168]	154	1			T125	1		T114	1		T191	5
len_datapath_width	13353	1			T1	6		T7	11		T8	6
len_2_63	122250	1			T1	57		T7	94		T8	27
len_1	54	1			T7	1		T148	1		T193	1