Group : kmac_env_pkg::kmac_env_cov::state_read_mask_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : kmac_env_pkg::kmac_env_cov::state_read_mask_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv



Summary for Group kmac_env_pkg::kmac_env_cov::state_read_mask_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 8 0 8 100.00


Variables for Group kmac_env_pkg::kmac_env_cov::state_read_mask_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
share 2 0 2 100.00 100 1 1 2
state_read_mask 4 0 4 100.00 100 1 1 0


Crosses for Group kmac_env_pkg::kmac_env_cov::state_read_mask_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
state_mask_share_cross 8 0 8 100.00 100 1 1 0


Summary for Variable share

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for share

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8183498 1 T1 23224 T7 41618 T16 4500
auto[1] 8183498 1 T1 23224 T7 41618 T16 4500



Summary for Variable state_read_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for state_read_mask

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
word_access 16231554 1 T1 46214 T7 82836 T16 8958
triple_byte_access 45212 1 T1 82 T7 134 T16 16
halfword_access 45224 1 T1 72 T7 134 T16 14
byte_access 45006 1 T1 80 T7 132 T16 12



Summary for Cross state_mask_share_cross

Samples crossed: share state_read_mask
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 0 8 100.00


Automatically Generated Cross Bins for state_mask_share_cross

Bins
sharestate_read_maskCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] word_access 8115777 1 T1 23107 T7 41418 T16 4479
auto[0] triple_byte_access 22606 1 T1 41 T7 67 T16 8
auto[0] halfword_access 22612 1 T1 36 T7 67 T16 7
auto[0] byte_access 22503 1 T1 40 T7 66 T16 6
auto[1] word_access 8115777 1 T1 23107 T7 41418 T16 4479
auto[1] triple_byte_access 22606 1 T1 41 T7 67 T16 8
auto[1] halfword_access 22612 1 T1 36 T7 67 T16 7
auto[1] byte_access 22503 1 T1 40 T7 66 T16 6

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%