Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8183498 |
1 |
|
|
T1 |
23224 |
|
T7 |
41618 |
|
T16 |
4500 |
auto[1] |
8183498 |
1 |
|
|
T1 |
23224 |
|
T7 |
41618 |
|
T16 |
4500 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
16231554 |
1 |
|
|
T1 |
46214 |
|
T7 |
82836 |
|
T16 |
8958 |
triple_byte_access |
45212 |
1 |
|
|
T1 |
82 |
|
T7 |
134 |
|
T16 |
16 |
halfword_access |
45224 |
1 |
|
|
T1 |
72 |
|
T7 |
134 |
|
T16 |
14 |
byte_access |
45006 |
1 |
|
|
T1 |
80 |
|
T7 |
132 |
|
T16 |
12 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
8115777 |
1 |
|
|
T1 |
23107 |
|
T7 |
41418 |
|
T16 |
4479 |
auto[0] |
triple_byte_access |
22606 |
1 |
|
|
T1 |
41 |
|
T7 |
67 |
|
T16 |
8 |
auto[0] |
halfword_access |
22612 |
1 |
|
|
T1 |
36 |
|
T7 |
67 |
|
T16 |
7 |
auto[0] |
byte_access |
22503 |
1 |
|
|
T1 |
40 |
|
T7 |
66 |
|
T16 |
6 |
auto[1] |
word_access |
8115777 |
1 |
|
|
T1 |
23107 |
|
T7 |
41418 |
|
T16 |
4479 |
auto[1] |
triple_byte_access |
22606 |
1 |
|
|
T1 |
41 |
|
T7 |
67 |
|
T16 |
8 |
auto[1] |
halfword_access |
22612 |
1 |
|
|
T1 |
36 |
|
T7 |
67 |
|
T16 |
7 |
auto[1] |
byte_access |
22503 |
1 |
|
|
T1 |
40 |
|
T7 |
66 |
|
T16 |
6 |