Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	59119304	1			T3	1300		T6	5095		T17	328
all_values[1]	59119304	1			T3	1300		T6	5095		T17	328
all_values[2]	59119304	1			T3	1300		T6	5095		T17	328

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

511549

1

T3

246

T6

288

T17

7

auto[1]

176846363

1

T3

3654

T6

14997

T17

977

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

176551704

1

T3

3852

T6

15138

T17

945

auto[1]

806208

1

T3

48

T6

147

T17

39

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	179558	1			T3	121		T37	37		T70	79
all_values[0]	auto[0]	auto[1]	1837	1			T3	2		T37	6		T70	6
all_values[0]	auto[1]	auto[0]	58671010	1			T3	1163		T6	5046		T17	315
all_values[0]	auto[1]	auto[1]	266899	1			T3	14		T6	49		T17	13
all_values[1]	auto[0]	auto[0]	177611	1			T6	287		T7	129		T32	2
all_values[1]	auto[0]	auto[1]	1385	1			T6	1		T7	1		T32	1
all_values[1]	auto[1]	auto[0]	58672957	1			T3	1284		T6	4759		T17	315
all_values[1]	auto[1]	auto[1]	267351	1			T3	16		T6	48		T17	13
all_values[2]	auto[0]	auto[0]	149737	1			T3	121		T17	6		T7	129
all_values[2]	auto[0]	auto[1]	1421	1			T3	2		T17	1		T7	1
all_values[2]	auto[1]	auto[0]	58700831	1			T3	1163		T6	5046		T17	309
all_values[2]	auto[1]	auto[1]	267315	1			T3	14		T6	49		T17	12