Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
169862 |
1 |
|
|
T2 |
2 |
|
T3 |
18 |
|
T6 |
2 |
auto[1] |
200702 |
1 |
|
|
T6 |
72 |
|
T37 |
350 |
|
T70 |
16 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
92631 |
1 |
|
|
T2 |
1 |
|
T3 |
4 |
|
T6 |
25 |
lower_val |
91211 |
1 |
|
|
T3 |
4 |
|
T6 |
14 |
|
T17 |
6 |
zero_val |
1384 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
134952 |
1 |
|
|
T3 |
4 |
|
T6 |
16 |
|
T17 |
8 |
lower_val |
134582 |
1 |
|
|
T3 |
14 |
|
T6 |
28 |
|
T17 |
10 |
zero_val |
101030 |
1 |
|
|
T2 |
2 |
|
T6 |
30 |
|
T37 |
168 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
21160 |
1 |
|
|
T3 |
1 |
|
T17 |
2 |
|
T7 |
37 |
higher_val |
higher_val |
auto[1] |
12502 |
1 |
|
|
T6 |
6 |
|
T37 |
29 |
|
T70 |
1 |
higher_val |
lower_val |
auto[0] |
21024 |
1 |
|
|
T3 |
3 |
|
T17 |
1 |
|
T7 |
38 |
higher_val |
lower_val |
auto[1] |
12529 |
1 |
|
|
T6 |
8 |
|
T37 |
30 |
|
T39 |
15 |
higher_val |
zero_val |
auto[0] |
71 |
1 |
|
|
T2 |
1 |
|
T134 |
1 |
|
T60 |
1 |
higher_val |
zero_val |
auto[1] |
25345 |
1 |
|
|
T6 |
11 |
|
T37 |
59 |
|
T70 |
2 |
lower_val |
higher_val |
auto[0] |
20522 |
1 |
|
|
T17 |
3 |
|
T7 |
33 |
|
T32 |
97 |
lower_val |
higher_val |
auto[1] |
12573 |
1 |
|
|
T6 |
2 |
|
T37 |
25 |
|
T39 |
15 |
lower_val |
lower_val |
auto[0] |
20914 |
1 |
|
|
T3 |
4 |
|
T17 |
3 |
|
T7 |
37 |
lower_val |
lower_val |
auto[1] |
12248 |
1 |
|
|
T6 |
8 |
|
T37 |
25 |
|
T39 |
11 |
lower_val |
zero_val |
auto[0] |
74 |
1 |
|
|
T37 |
1 |
|
T39 |
1 |
|
T20 |
1 |
lower_val |
zero_val |
auto[1] |
24880 |
1 |
|
|
T6 |
4 |
|
T37 |
38 |
|
T70 |
5 |
zero_val |
higher_val |
auto[0] |
416 |
1 |
|
|
T32 |
2 |
|
T8 |
1 |
|
T48 |
2 |
zero_val |
higher_val |
auto[1] |
98 |
1 |
|
|
T63 |
1 |
|
T190 |
1 |
|
T168 |
2 |
zero_val |
lower_val |
auto[0] |
427 |
1 |
|
|
T3 |
1 |
|
T17 |
1 |
|
T7 |
1 |
zero_val |
lower_val |
auto[1] |
89 |
1 |
|
|
T63 |
2 |
|
T169 |
2 |
|
T77 |
1 |
zero_val |
zero_val |
auto[0] |
224 |
1 |
|
|
T2 |
1 |
|
T6 |
1 |
|
T37 |
1 |
zero_val |
zero_val |
auto[1] |
130 |
1 |
|
|
T37 |
2 |
|
T63 |
1 |
|
T190 |
1 |