Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	5111	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	6164	1			T32	19		T48	19		T38	24
len_5001_7500	10784	1			T32	18		T48	18		T38	24
len_2501_5000	6669	1			T32	18		T48	18		T38	24
len_1025_2500	3921	1			T32	11		T48	11		T38	14
len_769_1024	5594	1			T3	1		T6	10		T7	38
len_513_768	6177	1			T3	3		T6	6		T7	31
len_257_512	9926	1			T3	3		T6	7		T7	34
len_0_256	124693	1			T3	2		T6	11		T17	9
len_keccak_block_sizes[72]	494	1			T32	2		T48	2		T38	2
len_keccak_block_sizes[104]	397	1			T32	2		T48	2		T38	2
len_keccak_block_sizes[136]	289	1			T32	2		T48	2		T167	2
len_keccak_block_sizes[144]	198	1			T135	3		T63	3		T201	2
len_keccak_block_sizes[168]	121	1			T8	1		T135	3		T14	1
len_1	534	1			T32	2		T48	2		T37	2
len_0	919	1			T32	2		T48	2		T37	6