Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	59119304	1			T3	1300		T6	5095		T17	328
all_pins[1]	59119304	1			T3	1300		T6	5095		T17	328
all_pins[2]	59119304	1			T3	1300		T6	5095		T17	328

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	176836924	1			T3	3886		T6	15114		T17	971
values[0x1]	520988	1			T3	14		T6	171		T17	13
transitions[0x0=>0x1]	519233	1			T3	14		T6	171		T17	13
transitions[0x1=>0x0]	519263	1			T3	14		T6	171		T17	13

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	58852405	1			T3	1286		T6	5046		T17	315
all_pins[0]	values[0x1]	266899	1			T3	14		T6	49		T17	13
all_pins[0]	transitions[0x0=>0x1]	266884	1			T3	14		T6	49		T17	13
all_pins[0]	transitions[0x1=>0x0]	5569	1			T6	15		T7	39		T70	1
all_pins[1]	values[0x0]	59113720	1			T3	1300		T6	5080		T17	328
all_pins[1]	values[0x1]	5584	1			T6	15		T7	39		T70	1
all_pins[1]	transitions[0x0=>0x1]	5364	1			T6	15		T7	39		T70	1
all_pins[1]	transitions[0x1=>0x0]	248285	1			T6	107		T8	1062		T19	589
all_pins[2]	values[0x0]	58870799	1			T3	1300		T6	4988		T17	328
all_pins[2]	values[0x1]	248505	1			T6	107		T8	1062		T19	589
all_pins[2]	transitions[0x0=>0x1]	246985	1			T6	107		T8	1062		T19	589
all_pins[2]	transitions[0x1=>0x0]	265409	1			T3	14		T6	49		T17	13