Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	621	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	4788	1			T3	1		T6	6		T7	18
len_601_800	11443	1			T3	4		T6	8		T7	46
len_401_600	7483	1			T3	2		T6	5		T7	38
len_201_400	9008	1			T3	2		T6	4		T7	22
len_65_200	28618	1			T6	3		T7	3		T8	10
len_min_for_xof_require_squeeze	387	1			T37	1		T135	9		T35	1
len_keccak_block_sizes[72]	270	1			T37	1		T135	9		T63	5
len_keccak_block_sizes[104]	273	1			T135	9		T61	1		T63	5
len_keccak_block_sizes[136]	271	1			T21	1		T135	9		T63	5
len_keccak_block_sizes[144]	151	1			T8	1		T18	1		T63	5
len_keccak_block_sizes[168]	151	1			T37	2		T59	1		T63	5
len_datapath_width	13618	1			T17	3		T7	1		T8	1
len_2_63	108086	1			T6	2		T17	6		T7	31
len_1	54	1			T37	1		T61	1		T202	1