Summary for Variable in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for in_app_keymgr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
183506 |
1 |
|
|
T2 |
1 |
|
T3 |
8 |
|
T6 |
37 |
auto[1] |
3096 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T6 |
1 |
Summary for Variable kmac_mode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_mode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
151796 |
1 |
|
|
T3 |
2 |
|
T6 |
10 |
|
T7 |
85 |
auto[1] |
34806 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
6 |
Summary for Variable sideload
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for sideload
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
173273 |
1 |
|
|
T2 |
1 |
|
T6 |
32 |
|
T17 |
9 |
auto[1] |
13329 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
8 |
Summary for Cross sideload_cross
Samples crossed: sideload kmac_mode in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins for sideload_cross
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
sw_kmac_valid_sideload |
13329 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
8 |
sw_kmac_invalid_sideload |
173273 |
1 |
|
|
T2 |
1 |
|
T6 |
32 |
|
T17 |
9 |
app_valid_sideload |
13329 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
8 |
app_invalid_sideload |
173273 |
1 |
|
|
T2 |
1 |
|
T6 |
32 |
|
T17 |
9 |