Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	63244009	1			T1	110169		T3	461730		T17	317
all_values[1]	63244009	1			T1	110169		T3	461730		T17	317
all_values[2]	63244009	1			T1	110169		T3	461730		T17	317

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

521396

1

T1

3

T17

16

T34

51

auto[1]

189210631

1

T1

330504

T3

138519

T17

935

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

188878503

1

T1

329385

T3

137503

T17

912

auto[1]

853524

1

T1

1122

T3

10152

T17

39

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	192460	1			T1	1		T17	6		T34	15
all_values[0]	auto[0]	auto[1]	1947	1			T1	2		T17	2		T34	4
all_values[0]	auto[1]	auto[0]	62767041	1			T1	109794		T3	458346		T17	298
all_values[0]	auto[1]	auto[1]	282561	1			T1	372		T3	3384		T17	11
all_values[1]	auto[0]	auto[0]	134540	1			T34	15		T7	754		T13	23
all_values[1]	auto[0]	auto[1]	1446	1			T34	4		T7	4		T9	2
all_values[1]	auto[1]	auto[0]	62824961	1			T1	109795		T3	458346		T17	304
all_values[1]	auto[1]	auto[1]	283062	1			T1	374		T3	3384		T17	13
all_values[2]	auto[0]	auto[0]	189433	1			T17	6		T34	11		T7	252
all_values[2]	auto[0]	auto[1]	1570	1			T17	2		T34	2		T7	2
all_values[2]	auto[1]	auto[0]	62770068	1			T1	109795		T3	458346		T17	298
all_values[2]	auto[1]	auto[1]	282938	1			T1	374		T3	3384		T17	11