Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
202866 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
4530 |
auto[1] |
190510 |
1 |
|
|
T1 |
490 |
|
T17 |
16 |
|
T36 |
618 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
99811 |
1 |
|
|
T1 |
108 |
|
T3 |
1164 |
|
T17 |
4 |
lower_val |
96780 |
1 |
|
|
T1 |
126 |
|
T2 |
1 |
|
T3 |
1174 |
zero_val |
1411 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
3 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
148412 |
1 |
|
|
T1 |
124 |
|
T3 |
2300 |
|
T17 |
6 |
lower_val |
148734 |
1 |
|
|
T1 |
116 |
|
T3 |
2230 |
|
T17 |
2 |
zero_val |
96230 |
1 |
|
|
T1 |
252 |
|
T2 |
2 |
|
T17 |
10 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
25529 |
1 |
|
|
T3 |
611 |
|
T34 |
55 |
|
T7 |
39 |
higher_val |
higher_val |
auto[1] |
12193 |
1 |
|
|
T1 |
33 |
|
T17 |
3 |
|
T36 |
30 |
higher_val |
lower_val |
auto[0] |
25802 |
1 |
|
|
T3 |
553 |
|
T34 |
37 |
|
T7 |
47 |
higher_val |
lower_val |
auto[1] |
11881 |
1 |
|
|
T1 |
24 |
|
T36 |
38 |
|
T38 |
4 |
higher_val |
zero_val |
auto[0] |
82 |
1 |
|
|
T9 |
1 |
|
T51 |
1 |
|
T69 |
1 |
higher_val |
zero_val |
auto[1] |
24324 |
1 |
|
|
T1 |
51 |
|
T17 |
1 |
|
T36 |
94 |
lower_val |
higher_val |
auto[0] |
24858 |
1 |
|
|
T3 |
585 |
|
T34 |
38 |
|
T7 |
61 |
lower_val |
higher_val |
auto[1] |
11823 |
1 |
|
|
T1 |
28 |
|
T17 |
2 |
|
T36 |
48 |
lower_val |
lower_val |
auto[0] |
25005 |
1 |
|
|
T3 |
589 |
|
T34 |
33 |
|
T7 |
34 |
lower_val |
lower_val |
auto[1] |
11529 |
1 |
|
|
T1 |
34 |
|
T36 |
35 |
|
T37 |
1 |
lower_val |
zero_val |
auto[0] |
85 |
1 |
|
|
T2 |
1 |
|
T8 |
1 |
|
T18 |
1 |
lower_val |
zero_val |
auto[1] |
23480 |
1 |
|
|
T1 |
64 |
|
T17 |
2 |
|
T36 |
68 |
zero_val |
higher_val |
auto[0] |
427 |
1 |
|
|
T7 |
1 |
|
T39 |
1 |
|
T10 |
1 |
zero_val |
higher_val |
auto[1] |
87 |
1 |
|
|
T9 |
1 |
|
T50 |
1 |
|
T19 |
1 |
zero_val |
lower_val |
auto[0] |
433 |
1 |
|
|
T3 |
3 |
|
T34 |
1 |
|
T13 |
1 |
zero_val |
lower_val |
auto[1] |
94 |
1 |
|
|
T19 |
1 |
|
T188 |
1 |
|
T60 |
1 |
zero_val |
zero_val |
auto[0] |
249 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T17 |
1 |
zero_val |
zero_val |
auto[1] |
121 |
1 |
|
|
T9 |
1 |
|
T50 |
1 |
|
T16 |
3 |