Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	63244009	1			T1	110169		T3	461730		T17	317
all_pins[1]	63244009	1			T1	110169		T3	461730		T17	317
all_pins[2]	63244009	1			T1	110169		T3	461730		T17	317

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	189163241	1			T1	330135		T3	138180		T17	939
values[0x1]	568786	1			T1	372		T3	3384		T17	12
transitions[0x0=>0x1]	566883	1			T1	372		T3	3384		T17	12
transitions[0x1=>0x0]	566910	1			T1	372		T3	3384		T17	12

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	62961448	1			T1	109797		T3	458346		T17	306
all_pins[0]	values[0x1]	282561	1			T1	372		T3	3384		T17	11
all_pins[0]	transitions[0x0=>0x1]	282546	1			T1	372		T3	3384		T17	11
all_pins[0]	transitions[0x1=>0x0]	5610	1			T17	1		T7	73		T39	40
all_pins[1]	values[0x0]	63238384	1			T1	110169		T3	461730		T17	316
all_pins[1]	values[0x1]	5625	1			T17	1		T7	73		T39	40
all_pins[1]	transitions[0x0=>0x1]	5460	1			T17	1		T7	73		T39	40
all_pins[1]	transitions[0x1=>0x0]	280435	1			T7	1232		T10	708		T45	123
all_pins[2]	values[0x0]	62963409	1			T1	110169		T3	461730		T17	317
all_pins[2]	values[0x1]	280600	1			T7	1232		T10	708		T45	123
all_pins[2]	transitions[0x0=>0x1]	278877	1			T7	1232		T10	704		T45	122
all_pins[2]	transitions[0x1=>0x0]	280865	1			T1	372		T3	3384		T17	11