Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	621	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	4932	1			T7	28		T9	9		T39	30
len_601_800	11503	1			T7	38		T9	29		T39	51
len_401_600	7547	1			T7	35		T9	12		T39	40
len_201_400	7898	1			T3	251		T7	12		T9	6
len_65_200	30971	1			T3	680		T34	73		T7	4
len_min_for_xof_require_squeeze	410	1			T3	10		T34	1		T68	1
len_keccak_block_sizes[72]	310	1			T3	5		T34	2		T109	2
len_keccak_block_sizes[104]	332	1			T3	5		T38	1		T68	2
len_keccak_block_sizes[136]	323	1			T3	5		T68	1		T109	1
len_keccak_block_sizes[144]	108	1			T3	5		T193	1		T194	5
len_keccak_block_sizes[168]	113	1			T3	5		T34	1		T195	1
len_datapath_width	13627	1			T1	246		T3	5		T17	3
len_2_63	117956	1			T3	1329		T17	6		T34	69
len_1	43	1			T34	2		T68	1		T19	1