Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7799108 |
1 |
|
|
T1 |
3936 |
|
T3 |
47900 |
|
T17 |
96 |
auto[1] |
7799067 |
1 |
|
|
T1 |
3936 |
|
T3 |
47900 |
|
T17 |
96 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
15475637 |
1 |
|
|
T1 |
7872 |
|
T3 |
93928 |
|
T17 |
192 |
triple_byte_access |
40956 |
1 |
|
|
T3 |
620 |
|
T34 |
70 |
|
T7 |
90 |
halfword_access |
40768 |
1 |
|
|
T3 |
632 |
|
T34 |
68 |
|
T7 |
66 |
byte_access |
40814 |
1 |
|
|
T3 |
620 |
|
T34 |
70 |
|
T7 |
66 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
7737839 |
1 |
|
|
T1 |
3936 |
|
T3 |
46964 |
|
T17 |
96 |
auto[0] |
triple_byte_access |
20478 |
1 |
|
|
T3 |
310 |
|
T34 |
35 |
|
T7 |
45 |
auto[0] |
halfword_access |
20384 |
1 |
|
|
T3 |
316 |
|
T34 |
34 |
|
T7 |
33 |
auto[0] |
byte_access |
20407 |
1 |
|
|
T3 |
310 |
|
T34 |
35 |
|
T7 |
33 |
auto[1] |
word_access |
7737798 |
1 |
|
|
T1 |
3936 |
|
T3 |
46964 |
|
T17 |
96 |
auto[1] |
triple_byte_access |
20478 |
1 |
|
|
T3 |
310 |
|
T34 |
35 |
|
T7 |
45 |
auto[1] |
halfword_access |
20384 |
1 |
|
|
T3 |
316 |
|
T34 |
34 |
|
T7 |
33 |
auto[1] |
byte_access |
20407 |
1 |
|
|
T3 |
310 |
|
T34 |
35 |
|
T7 |
33 |