Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	64655677	1			T1	113490		T2	224535		T3	17327
all_values[1]	64655677	1			T1	113490		T2	224535		T3	17327
all_values[2]	64655677	1			T1	113490		T2	224535		T3	17327

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

392478

1

T1

7

T2

19

T3

282

auto[1]

193574553

1

T1

340463

T2

673586

T3

51699

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

193060920

1

T1

339411

T2

671823

T3

51423

auto[1]

906111

1

T1

1059

T2

1782

T3

558

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	138420	1			T3	117		T13	1		T9	666
all_values[0]	auto[0]	auto[1]	1778	1			T3	4		T9	16		T18	2
all_values[0]	auto[1]	auto[0]	64215220	1			T1	113137		T2	223941		T3	17024
all_values[0]	auto[1]	auto[1]	300259	1			T1	353		T2	594		T3	182
all_values[1]	auto[0]	auto[0]	130925	1			T1	5		T2	13		T13	1
all_values[1]	auto[0]	auto[1]	1474	1			T1	2		T2	6		T7	2
all_values[1]	auto[1]	auto[0]	64222715	1			T1	113132		T2	223928		T3	17141
all_values[1]	auto[1]	auto[1]	300563	1			T1	351		T2	588		T3	186
all_values[2]	auto[0]	auto[0]	118563	1			T3	156		T13	1		T38	17
all_values[2]	auto[0]	auto[1]	1318	1			T3	5		T38	2		T39	3
all_values[2]	auto[1]	auto[0]	64235077	1			T1	113137		T2	223941		T3	16985
all_values[2]	auto[1]	auto[1]	300719	1			T1	353		T2	594		T3	181