Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
197978 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
2 |
auto[1] |
217268 |
1 |
|
|
T1 |
490 |
|
T2 |
778 |
|
T3 |
244 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
104468 |
1 |
|
|
T1 |
116 |
|
T2 |
198 |
|
T3 |
74 |
lower_val |
102850 |
1 |
|
|
T1 |
146 |
|
T2 |
202 |
|
T3 |
62 |
zero_val |
1434 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
153092 |
1 |
|
|
T1 |
124 |
|
T2 |
214 |
|
T3 |
48 |
lower_val |
153056 |
1 |
|
|
T1 |
144 |
|
T2 |
186 |
|
T3 |
64 |
zero_val |
109098 |
1 |
|
|
T1 |
224 |
|
T2 |
380 |
|
T3 |
134 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
24748 |
1 |
|
|
T33 |
555 |
|
T13 |
1 |
|
T9 |
17 |
higher_val |
higher_val |
auto[1] |
13725 |
1 |
|
|
T1 |
28 |
|
T2 |
64 |
|
T3 |
18 |
higher_val |
lower_val |
auto[0] |
24734 |
1 |
|
|
T33 |
585 |
|
T7 |
1 |
|
T9 |
16 |
higher_val |
lower_val |
auto[1] |
13808 |
1 |
|
|
T1 |
34 |
|
T2 |
42 |
|
T3 |
21 |
higher_val |
zero_val |
auto[0] |
86 |
1 |
|
|
T2 |
1 |
|
T34 |
1 |
|
T61 |
1 |
higher_val |
zero_val |
auto[1] |
27367 |
1 |
|
|
T1 |
54 |
|
T2 |
91 |
|
T3 |
35 |
lower_val |
higher_val |
auto[0] |
24245 |
1 |
|
|
T33 |
525 |
|
T9 |
8 |
|
T87 |
105 |
lower_val |
higher_val |
auto[1] |
13666 |
1 |
|
|
T1 |
32 |
|
T2 |
53 |
|
T3 |
11 |
lower_val |
lower_val |
auto[0] |
24569 |
1 |
|
|
T33 |
579 |
|
T8 |
1 |
|
T9 |
14 |
lower_val |
lower_val |
auto[1] |
13252 |
1 |
|
|
T1 |
43 |
|
T2 |
50 |
|
T3 |
14 |
lower_val |
zero_val |
auto[0] |
78 |
1 |
|
|
T36 |
1 |
|
T9 |
1 |
|
T14 |
1 |
lower_val |
zero_val |
auto[1] |
27040 |
1 |
|
|
T1 |
71 |
|
T2 |
99 |
|
T3 |
37 |
zero_val |
higher_val |
auto[0] |
457 |
1 |
|
|
T33 |
3 |
|
T13 |
1 |
|
T9 |
1 |
zero_val |
higher_val |
auto[1] |
106 |
1 |
|
|
T9 |
1 |
|
T38 |
1 |
|
T39 |
2 |
zero_val |
lower_val |
auto[0] |
420 |
1 |
|
|
T33 |
2 |
|
T7 |
1 |
|
T8 |
1 |
zero_val |
lower_val |
auto[1] |
80 |
1 |
|
|
T173 |
1 |
|
T20 |
2 |
|
T40 |
2 |
zero_val |
zero_val |
auto[0] |
233 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
zero_val |
zero_val |
auto[1] |
138 |
1 |
|
|
T38 |
1 |
|
T40 |
2 |
|
T212 |
1 |